The Experts below are selected from a list of 6642 Experts worldwide ranked by ideXlab platform
Prabhas Chongstitvatana - One of the best experts on this subject based on the ideXlab platform.
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Instruction Packing for a 32-Bit Stack-Based Processor
2007Co-Authors: Witcharat Lertteerawattana, Tanes Jedsadawaranon, Prabhas ChongstitvatanaAbstract:Abstract- This work proposed a design and development of a 32-Bit stack-based processor for embedded systems. A reference processor has a 32-Bit stack-based Instruction set. This work proposed a technique of Instruction packing which packs several Instructions into one 32-Bit Instruction unit. Therefore, the Instruction size is reduced. The result of the experiment shows that the proposed technique achieves around 30 % reduction in code size
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Instruction packing for a 32 bit stack based processor
2007Co-Authors: Prabhas ChongstitvatanaAbstract:This work proposed a design and development of a 32-Bit stack-based processor for embedded systems. A reference processor has a 32-Bit stack-based Instruction set. This work proposed a technique of Instruction packing which packs several Instructions into one 32-Bit Instruction unit. Ther efore, the Instruction size is reduced. The result of the experiment shows that the proposed technique achieves around 30% reduction in code size. The TS register stores the top of stack value. The SP register stores the pointer to the second value in the stack (below the top of stack). FP register, as its name, keeps the frame pointer. NX and FF registers are used when some Instruction needs a temporary storage during comput ing the result from ALU. The AA register stores the array pointer for dynamic memory allocation. The data path consists o f one ALU that connects to the register bank and the resu lt from ALU is connected to tbus and tbus connects to the register bank. The PC register is designed with an auto- increment module, so fetching Instruction can be done in one clock cycle. It also can be loaded with the value PC+arg or tbus. The memory interface is through Bus Interface Unit (BIU). The BIU connects data input (din) and output (dout) from to memory. The din can be selected from TS or FP. ALU is connected with two multiplexers p1 and p2 which p1 interfaces to four registers TS, SP, FP and NX and p2 links with FF and the Instruction argument value.
Witcharat Lertteerawattana - One of the best experts on this subject based on the ideXlab platform.
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Instruction Packing for a 32-Bit Stack-Based Processor
2007Co-Authors: Witcharat Lertteerawattana, Tanes Jedsadawaranon, Prabhas ChongstitvatanaAbstract:Abstract- This work proposed a design and development of a 32-Bit stack-based processor for embedded systems. A reference processor has a 32-Bit stack-based Instruction set. This work proposed a technique of Instruction packing which packs several Instructions into one 32-Bit Instruction unit. Therefore, the Instruction size is reduced. The result of the experiment shows that the proposed technique achieves around 30 % reduction in code size
Tanes Jedsadawaranon - One of the best experts on this subject based on the ideXlab platform.
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Instruction Packing for a 32-Bit Stack-Based Processor
2007Co-Authors: Witcharat Lertteerawattana, Tanes Jedsadawaranon, Prabhas ChongstitvatanaAbstract:Abstract- This work proposed a design and development of a 32-Bit stack-based processor for embedded systems. A reference processor has a 32-Bit stack-based Instruction set. This work proposed a technique of Instruction packing which packs several Instructions into one 32-Bit Instruction unit. Therefore, the Instruction size is reduced. The result of the experiment shows that the proposed technique achieves around 30 % reduction in code size
Greg Jaxon - One of the best experts on this subject based on the ideXlab platform.
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Cedar Synchronization Processor Instruction Set Reference
2007Co-Authors: David Pointer, Greg JaxonAbstract:This document explicitly defines the Cedar synchronization (sync) processor Instruction coding and operational details from the programmer's point of view. It is based on [1]. There are no longer any don't care bits in the Instruction bit pattern nor are there possible duplicate Instructions with different bit patterns. In addition, some redundant sync Instructions mentioned in [1] have been deleted. These are summarized in Appendix A. Some uses of the sync processor for data synchronization and data structure manipulation are described in [2] [3] [4] [5]. The bit patterns for each Instruction word defined in this document are all usable bit patterns of the 32-Bit Instruction word. All bit patterns of the Instruction word that are not defined in this document are reserved and may not be used in any manner. Each sync processor Instruction is atomic. Each pseudo-C code segment describing an Instruction's execution may therefore be considered to be atomic. C language constructs and operators [6] are used throughout this document. Alliant Concentrix C extensions to the standard C language used in this document are described in [7]. The variable declarations for the pseudo-C code in each section are: unsigned long *tas_target; /* address of 32-Bit key in global memory */ unsigned long key; /* 32-Bit global memory word */ unsigned long Instruction; /* the sync Instruction */ unsigned long operand1; /* 32-Bit value for condition test */ unsigned long operand2; /* 32-Bit immediate value (data) */ int n_flag; /* N flag in CE condition code register */ double write_data; /* 64-bit data for key/data write */ unsigned long short_const; /* used for building constant (ADDIS, SUBIS) */ struct gib Gibmap; /* structure of type gib (defined in gib.h) *
Loh K. K. L. - One of the best experts on this subject based on the ideXlab platform.
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eQASM: An Executable Quantum Instruction Set Architecture
2019Co-Authors: Fu X., Riesebos L., Rol M. A., Van Straten J., Van Someren J., Khammassi N., Vermeulen R. F. L., Loh K. K. L.Abstract:A widely-used quantum programming paradigm comprises of both the data flow and control flow. Existing quantum hardware cannot well support the control flow, significantly limiting the range of quantum software executable on the hardware. By analyzing the constraints in the control microarchitecture, we found that existing quantum assembly languages are either too high-level or too restricted to support comprehensive flow control on the hardware. Also, as observed with the quantum microInstruction set QuMIS, the quantum Instruction set architecture (QISA) design may suffer from limited scalability and flexibility because of microarchitectural constraints. It is an open challenge to design a scalable and flexible QISA which provides a comprehensive abstraction of the quantum hardware. In this paper, we propose an executable QISA, called eQASM, that can be translated from quantum assembly language (QASM), supports comprehensive quantum program flow control, and is executed on a quantum control microarchitecture. With efficient timing specification, single-operation-multiple-qubit execution, and a very-long-Instruction-word architecture, eQASM presents better scalability than QuMIS. The definition of eQASM focuses on the assembly level to be expressive. Quantum operations are configured at compile time instead of being defined at QISA design time. We instantiate eQASM into a 32-Bit Instruction set targeting a seven-qubit superconducting quantum processor. We validate our design by performing several experiments on a two-qubit quantum processor.Comment: 13 pages, 8 figures; added abstract, re-positioned figure
