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Accessing Memory

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Alexandre Carissimi – One of the best experts on this subject based on the ideXlab platform.

  • Memory Access Characterization of OpenMP Workloads on a Multi-core NUMA Machine
    , 2010
    Co-Authors: Christiane Pousa Ribeiro, Alexandre Carissimi, Jean-françois Méhaut

    Abstract:

    Nowadays, on hierarchical shared Memory multiprocessors with Non-Uniform Memory Access (NUMA), the number of cores Accessing Memory banks is considerably high. Such accesses produce more stress on the Memory banks, generating load-balancing issues, Memory contention and remote accesses. In this context, it is important to have a good understanding of Memory access patterns and what are the inuences of data placement on such patterns. In this document, we have investigated Memory accesses behavior of microbenchmarks and benchmarks over a ccNUMA platform with multi-core processors. Additionally, we have evaluated a set of Memory policies that were used to place data among the machine Memory banks. Our results have shown that an appropriate selection of data placement, considering the Memory accesses, can generated great improvement gains.

  • Memory affinity management for numerical scientific applications over Multi-core Multiprocessors with Hierarchical Memory
    2010 IEEE International Symposium on Parallel & Distributed Processing Workshops and Phd Forum (IPDPSW), 2010
    Co-Authors: Christiane Pousa Ribeiro, Jean-françois Méhaut, Alexandre Carissimi

    Abstract:

    Nowadays, on Multi-core Multiprocessors with Hierarchical Memory (Non-Uniform Memory Access (NUMA) characteristics), the number of cores Accessing Memory banks is considerably high. Such accesses produce stress on the Memory banks, generating load-balancing issues, Memory contention and remote accesses. In this context, how to manage Memory accesses in an efficient fashion remains an important concern. To reduce Memory access costs, developers have to manage data placement on their application assuring Memory affinity. The problem is: How to guarantee Memory affinity for different applications/NUMA platforms and assure efficiency, portability, minimal or none source code changes (transparency) and fine control of Memory access patterns? In this Thesis, our research have led to the proposal of Minas: an efficient and portable Memory affinity management framework for NUMA platforms. Minas provides both explicit Memory affinity management and automatic one with good performance, architecture abstraction, minimal or none application source code modifications and fine control. We have evaluated its efficiency and portability by performing some experiments with numerical scientific HPC applications on NUMA platforms. The results have been compared with other solutions to manage Memory affinity.

  • IPDPS Workshops – Memory affinity management for numerical scientific applications over Multi-core Multiprocessors with Hierarchical Memory
    2010 IEEE International Symposium on Parallel & Distributed Processing Workshops and Phd Forum (IPDPSW), 2010
    Co-Authors: Christiane Pousa Ribeiro, Jean-françois Méhaut, Alexandre Carissimi

    Abstract:

    Nowadays, on Multi-core Multiprocessors with Hierarchical Memory (Non-Uniform Memory Access (NUMA) characteristics), the number of cores Accessing Memory banks is considerably high. Such accesses produce stress on the Memory banks, generating load-balancing issues, Memory contention and remote accesses. In this context, how to manage Memory accesses in an efficient fashion remains an important concern. To reduce Memory access costs, developers have to manage data placement on their application assuring Memory affinity. The problem is: How to guarantee Memory affinity for different applications/NUMA platforms and assure efficiency, portability, minimal or none source code changes (transparency) and fine control of Memory access patterns? In this Thesis, our research have led to the proposal of Minas: an efficient and portable Memory affinity management framework for NUMA platforms. Minas provides both explicit Memory affinity management and automatic one with good performance, architecture abstraction, minimal or none application source code modifications and fine control. We have evaluated its efficiency and portability by performing some experiments with numerical scientific HPC applications on NUMA platforms. The results have been compared with other solutions to manage Memory affinity.

Frank Bellosa – One of the best experts on this subject based on the ideXlab platform.

  • process cruise control throttling Memory access in a soft real time environment
    Symposium on Operating Systems Principles, 1997
    Co-Authors: Frank Bellosa

    Abstract:

    The advances in Memory technology concerning performance have not been able to keep pace with those in processor technology. Processors clocked with hundreds of megahertz exceed the speed of affordable Memory by factors. Caches can decouple the speed of the processing unit from the speed of the Memory system if applications show a high locality of reference. Unfortunately, operations on data streams – frequently found in soft real-time multimedia applications – do not show this benign behavior. Thus, applications working on data streams rely heavily upon a guaranteed Memory bandwidth to meet specific timing requirements. In multiprocessor systems the available Memory bandwidth is shared by all processing units and DMA devices. Consequently, the processing units can interfere and slow each other down when Accessing Memory. Up to now, this effect, called Memory preemption, is not covered by realtime operating systems using timer and I/O related information. Our novel approach to resource management is based on knowledge derived from counters in the Memory subsystem. We demonstrate that the use of information related to cacheand mainMemory access opens new dimensions of resource management in shared-Memory architectures. The introduction of Memory-bandwidth guarantees adds a further resource to capacityreservation models and therefore enhances the quality of service. Soft real-time processes can request Memory bandwidth guarantees. Processes without guarantees are throttled, so that they do not withhold valuable main Memory bandwidth from real-time applications. To dynamically slow down processes that exceed a certain number of main Memory operations per time frame, the TLB-miss handler executes additional NOP instructions. Thus, the TLB-fill will be delayed, fewer Memory pages can be touched and fewer cache misses per time frame will occur. This new mechanism, called Process Cruise Control, maintains the execution speed of soft real-time applications in a multiprocessor environment. Applications of other scheduling classes (e.g., Time-Sharing), which operate with low Memory demands, run at full speed, whereas applications with high Memory demands will be throttled in their speed of execution and executed with lower priority. Measurements conducted on a prototype implementation using the Solaris operating system clearly demonstrate the benefit of the Memory throttle for a video conferencing application running in a multiprogrammed multiprocessor environment.

Jean-françois Méhaut – One of the best experts on this subject based on the ideXlab platform.

  • Memory Access Characterization of OpenMP Workloads on a Multi-core NUMA Machine
    , 2010
    Co-Authors: Christiane Pousa Ribeiro, Alexandre Carissimi, Jean-françois Méhaut

    Abstract:

    Nowadays, on hierarchical shared Memory multiprocessors with Non-Uniform Memory Access (NUMA), the number of cores Accessing Memory banks is considerably high. Such accesses produce more stress on the Memory banks, generating load-balancing issues, Memory contention and remote accesses. In this context, it is important to have a good understanding of Memory access patterns and what are the inuences of data placement on such patterns. In this document, we have investigated Memory accesses behavior of microbenchmarks and benchmarks over a ccNUMA platform with multi-core processors. Additionally, we have evaluated a set of Memory policies that were used to place data among the machine Memory banks. Our results have shown that an appropriate selection of data placement, considering the Memory accesses, can generated great improvement gains.

  • Memory affinity management for numerical scientific applications over Multi-core Multiprocessors with Hierarchical Memory
    2010 IEEE International Symposium on Parallel & Distributed Processing Workshops and Phd Forum (IPDPSW), 2010
    Co-Authors: Christiane Pousa Ribeiro, Jean-françois Méhaut, Alexandre Carissimi

    Abstract:

    Nowadays, on Multi-core Multiprocessors with Hierarchical Memory (Non-Uniform Memory Access (NUMA) characteristics), the number of cores Accessing Memory banks is considerably high. Such accesses produce stress on the Memory banks, generating load-balancing issues, Memory contention and remote accesses. In this context, how to manage Memory accesses in an efficient fashion remains an important concern. To reduce Memory access costs, developers have to manage data placement on their application assuring Memory affinity. The problem is: How to guarantee Memory affinity for different applications/NUMA platforms and assure efficiency, portability, minimal or none source code changes (transparency) and fine control of Memory access patterns? In this Thesis, our research have led to the proposal of Minas: an efficient and portable Memory affinity management framework for NUMA platforms. Minas provides both explicit Memory affinity management and automatic one with good performance, architecture abstraction, minimal or none application source code modifications and fine control. We have evaluated its efficiency and portability by performing some experiments with numerical scientific HPC applications on NUMA platforms. The results have been compared with other solutions to manage Memory affinity.

  • IPDPS Workshops – Memory affinity management for numerical scientific applications over Multi-core Multiprocessors with Hierarchical Memory
    2010 IEEE International Symposium on Parallel & Distributed Processing Workshops and Phd Forum (IPDPSW), 2010
    Co-Authors: Christiane Pousa Ribeiro, Jean-françois Méhaut, Alexandre Carissimi

    Abstract:

    Nowadays, on Multi-core Multiprocessors with Hierarchical Memory (Non-Uniform Memory Access (NUMA) characteristics), the number of cores Accessing Memory banks is considerably high. Such accesses produce stress on the Memory banks, generating load-balancing issues, Memory contention and remote accesses. In this context, how to manage Memory accesses in an efficient fashion remains an important concern. To reduce Memory access costs, developers have to manage data placement on their application assuring Memory affinity. The problem is: How to guarantee Memory affinity for different applications/NUMA platforms and assure efficiency, portability, minimal or none source code changes (transparency) and fine control of Memory access patterns? In this Thesis, our research have led to the proposal of Minas: an efficient and portable Memory affinity management framework for NUMA platforms. Minas provides both explicit Memory affinity management and automatic one with good performance, architecture abstraction, minimal or none application source code modifications and fine control. We have evaluated its efficiency and portability by performing some experiments with numerical scientific HPC applications on NUMA platforms. The results have been compared with other solutions to manage Memory affinity.