The Experts below are selected from a list of 99 Experts worldwide ranked by ideXlab platform
K D Wise - One of the best experts on this subject based on the ideXlab platform.
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a 32 site 4 channel high density electrode array for a cochlear prosthesis
IEEE Journal of Solid-state Circuits, 2006Co-Authors: P T Bhatti, K D WiseAbstract:This paper describes a 32-site 4-channel high-density intracochlear electrode array. Combining MEMS-based processing technology with Active Circuitry, the thin-film device realizes a stimulating site density three times that of commercial systems, delivering 500 muA biphasic current levels with 8-bit resolution and less than 1% charge mismatch. The minimum pulsewidth is 4 mus, and the per-channel power dissipation is 2.5 mW from plusmn2.5 V. The Active circuit chip has a footprint of 2.4mmtimes2.9 mm. Serving as the end-effector of a cochlear prosthesis, the Active array also provides site-impedance measurement and position-sensing functions
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a 32 site 4 channel high density electrode array for a cochlear prosthesis
International Solid-State Circuits Conference, 2006Co-Authors: P T Bhatti, K D WiseAbstract:This paper describes a 32-site 4-channel high-density intracochlear electrode array. Combining MEMS-based processing technology with Active Circuitry, the thin-film device realizes a stimulating site density three times that of commercial systems, delivering 500 μA biphasic current levels with 8-bit resolution and less than 1% charge mismatch. The minimum pulsewidth is 4 μs, and the per-channel power dissipation is 2.5 mW from ±2.5 V. The Active circuit chip has a footprint of 2.4 mm x 2.9 mm. Serving as the end-effector of a cochlear prosthesis, the Active array also provides site-impedance measurement and position-sensing functions.
P T Bhatti - One of the best experts on this subject based on the ideXlab platform.
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a 32 site 4 channel high density electrode array for a cochlear prosthesis
IEEE Journal of Solid-state Circuits, 2006Co-Authors: P T Bhatti, K D WiseAbstract:This paper describes a 32-site 4-channel high-density intracochlear electrode array. Combining MEMS-based processing technology with Active Circuitry, the thin-film device realizes a stimulating site density three times that of commercial systems, delivering 500 muA biphasic current levels with 8-bit resolution and less than 1% charge mismatch. The minimum pulsewidth is 4 mus, and the per-channel power dissipation is 2.5 mW from plusmn2.5 V. The Active circuit chip has a footprint of 2.4mmtimes2.9 mm. Serving as the end-effector of a cochlear prosthesis, the Active array also provides site-impedance measurement and position-sensing functions
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a 32 site 4 channel high density electrode array for a cochlear prosthesis
International Solid-State Circuits Conference, 2006Co-Authors: P T Bhatti, K D WiseAbstract:This paper describes a 32-site 4-channel high-density intracochlear electrode array. Combining MEMS-based processing technology with Active Circuitry, the thin-film device realizes a stimulating site density three times that of commercial systems, delivering 500 μA biphasic current levels with 8-bit resolution and less than 1% charge mismatch. The minimum pulsewidth is 4 μs, and the per-channel power dissipation is 2.5 mW from ±2.5 V. The Active circuit chip has a footprint of 2.4 mm x 2.9 mm. Serving as the end-effector of a cochlear prosthesis, the Active array also provides site-impedance measurement and position-sensing functions.
Ali Hajimiri - One of the best experts on this subject based on the ideXlab platform.
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Designing Optimal Surface Currents for Efficient On-Chip mm-Wave Radiators With Active Circuitry
IEEE Transactions on Microwave Theory and Techniques, 2016Co-Authors: Kaushik Sengupta, Ali HajimiriAbstract:Integrated antennas have become the attrActive solution as the electromagnetic (EM) interface for mm-Wave and terahertz ICs. However, on-chip antennas lying at the interface between two different dielectrics (such as air and substrate) can channel most of its power into multiple nonradiative surface-wave modes, reducing efficiency drastically. In this paper, we consider the following problem: given a dielectric substrate, what is the theoretical optimal 2-D surface-current configuration that collectively suppresses surface waves and maximizes radiation efficiency with the desirable radiation pattern? This paper also discusses demonstrative examples of a circuit-EM codesign approach to realize the approximation of such current configurations. Measurement results of radiating arrays in CMOS at mm-Wave frequencies (250–300 GHz) are presented and compared with theoretical predictions.
Kaushik Sengupta - One of the best experts on this subject based on the ideXlab platform.
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Designing Optimal Surface Currents for Efficient On-Chip mm-Wave Radiators With Active Circuitry
IEEE Transactions on Microwave Theory and Techniques, 2016Co-Authors: Kaushik Sengupta, Ali HajimiriAbstract:Integrated antennas have become the attrActive solution as the electromagnetic (EM) interface for mm-Wave and terahertz ICs. However, on-chip antennas lying at the interface between two different dielectrics (such as air and substrate) can channel most of its power into multiple nonradiative surface-wave modes, reducing efficiency drastically. In this paper, we consider the following problem: given a dielectric substrate, what is the theoretical optimal 2-D surface-current configuration that collectively suppresses surface waves and maximizes radiation efficiency with the desirable radiation pattern? This paper also discusses demonstrative examples of a circuit-EM codesign approach to realize the approximation of such current configurations. Measurement results of radiating arrays in CMOS at mm-Wave frequencies (250–300 GHz) are presented and compared with theoretical predictions.
Troy Ruud - One of the best experts on this subject based on the ideXlab platform.
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use of harsh wire bonding to evaluate various bond pad structures
European Microelectronics and Packaging Conference, 2011Co-Authors: Steva Hunte, Jose Martinez, Marco Salas, Troy Ruud, Yce Rasmusse, Guy Iza, Daniel Vanderstraete, Cesa Salas, Steve Sheffield, Jaso SchofieldAbstract:IC bond pad structures having Al metallization and SiO 2 dielectric have been traditionally designed with full plates in underlying metallization layers, connected by vias. In addition, pads having bond over Active Circuitry (BOAC) which are much more sensitive to pad cracks, are likely present in the same IC. Cracks in the pad dielectric weaken the bond reliability and may cause electrical leakage or shorts to Circuitry under the pad. Cracks are more likely to occur during Cu wire bond due to higher bonding stress as compared to Au alloy wire bonding. Experimental data from bonding with 1mil Au or Cu wires reveals dramatic differences in pad robustness against cracking, depending upon the underlying metal structures and patterns. A “harsh” Au wire bond recipe is also developed to produce the stress effects of Cu wire bond in experiments without having to upgrade older bonding equipment for Cu wire. Cratering test after wire bond is used to evaluate pad cracking. Ball shear testing followed by a cratering test further reveals pad cracking tendencies. Design principles for increased pad robustness to cracking are developed based on the data. Reliability data verifies the effectiveness of the design principles. Proper design of interconnects beneath the pad can greatly increase pad robustness to cracking, allowing much more margin in bonding stress, enabling the option of Au or Cu wire bond on the same IC without pad cracking.
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bond over Active Circuitry design for reliability
International Symposium on Microelectronics, 2011Co-Authors: Stevan Hunter, Jose Martinez, Cesar Salas, Marco Salas, Jason Schofield, Steven Sheffield, Kyle Wilkins, Bryce Rasmussen, Troy RuudAbstract:This paper discusses layout design rules for successful Cu wire bond-over-Active-Circuitry (BOAC) in 0.18 micron and other IC technologies having Al metallization interconnects (two-level metal and up) in SiO2 dielectric, with W vias. The resulting bond pad structures effectively address BOAC pad reliability concerns, permitting Au or Cu wire bonding on relatively thin top metal. Cu wire bond is attrActive on BOAC designs for lower cost than Au wire, while improving the thermal capability of the product. But Cu wire bond has presented even more challenges than Au wire bond due to higher stress to the pads during bonding, typically leading to increases in underlying films deformation and cracking. The new BOAC pad layout rules are based on the physical thin films principles, substantiated and refined through analysis of a large volume of experimental and product qualification data in various IC technologies. Interconnect layout beneath pads which follows the BOAC design rules creates more robust bond pad s...
