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Address Generator

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Lingdi Ping – One of the best experts on this subject based on the ideXlab platform.

  • IPDPS – A Reconfigurable Computing Engine for Wavelet Transforms
    2007 IEEE International Parallel and Distributed Processing Symposium, 2007
    Co-Authors: Kang Sun, Xuezeng Pan, Lingdi Ping
    Abstract:

    In the past a few years, wavelet transforms have become a hot topic of research. Discrete and continuous wavelet transforms have been widely used in signal and multimedia processing. Due to the high performance and flexibility of reconfigurable computing systems, it is very attractive to design a re configurable architecture for discrete and continuous wavelet transform of wide range of wavelet filters. In this paper, a unified computation framework for discrete and continuous wavelet transform based on lifting scheme and a reconfigurable architecture that includes reconfigurable lifting step arrays and reconfigurable Address Generator are proposed. The unified framework is the theory basis of this system. The step array is the computing core of this engine. And the Address Generator supports several memory scan pattern which is used to generate memory access Addresses. In order to validate this architecture, an FPGA prototype is built based on Xilinx VirtexII FPGA to test the reconfiguration of 2-D discrete 5/3 and 9/7 transforms (defined in specification ofJPEG2000) and 2-D continuous Haar wavewavelet transform. Furthermore, a 3-level decomposition for a 512 times 512 grayscale image is performed and the results show that the decomposition can be finished within 12.16ms when running at 20MHz. It can be concluded that this design is applicable and scalable.

Kang Sun – One of the best experts on this subject based on the ideXlab platform.

  • IPDPS – A Reconfigurable Computing Engine for Wavelet Transforms
    2007 IEEE International Parallel and Distributed Processing Symposium, 2007
    Co-Authors: Kang Sun, Xuezeng Pan, Lingdi Ping
    Abstract:

    In the past a few years, wavelet transforms have become a hot topic of research. Discrete and continuous wavelet transforms have been widely used in signal and multimedia processing. Due to the high performance and flexibility of reconfigurable computing systems, it is very attractive to design a re configurable architecture for discrete and continuous wavelet transform of wide range of wavelet filters. In this paper, a unified computation framework for discrete and continuous wavelet transform based on lifting scheme and a reconfigurable architecture that includes reconfigurable lifting step arrays and reconfigurable Address Generator are proposed. The unified framework is the theory basis of this system. The step array is the computing core of this engine. And the Address Generator supports several memory scan pattern which is used to generate memory access Addresses. In order to validate this architecture, an FPGA prototype is built based on Xilinx VirtexII FPGA to test the reconfiguration of 2-D discrete 5/3 and 9/7 transforms (defined in specification ofJPEG2000) and 2-D continuous Haar wavelet transform. Furthermore, a 3-level decomposition for a 512 times 512 grayscale image is performed and the results show that the decomposition can be finished within 12.16ms when running at 20MHz. It can be concluded that this design is applicable and scalable.

Shabany – One of the best experts on this subject based on the ideXlab platform.

  • ISCAS – A low-complexity fully scalable interleaver/Address Generator based on a novel property of QPP interleavers
    2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017
    Co-Authors: Arash Ardakani, Shabany
    Abstract:

    5-th generation mobile networks aim the peak data rates in excess of few Gbs, which may appear to be challenging to achieve due to the existence of some blocks such as the turbo decoder. In fact, the interleaver is known to be a major challenging part of the turbo decoder due to its need to the parallel interleaved memory access. LTE uses Quadratic Permutation Polynomial (QPP) interleaver, which makes it suitable for the parallel decoding. In this paper, a new property of the QPP interleaver, called the correlated shifting property, is theoretically proved, leading to a fully scalable interleaver and a low-complexity Address Generator for an arbitrary order of parallelism. The proposed interleaver reduces the required Addresses in half. Moreover, the scalability of the proposed interleaver proves up to 51% lower power consumption compared to the best reported interleaver to-date.

Salil Kumar Sanyal – One of the best experts on this subject based on the ideXlab platform.

  • Memory Efficient LUT Based Address Generator for OFDM-WiMAX De-Interleaver
    International Journal of Electronics and Electrical Engineering, 2014
    Co-Authors: Bijoy Kumar Upadhyaya, Pranab Kumar Goswami, Salil Kumar Sanyal
    Abstract:

    In this paper, a memory efficient Look-up Table (LUT) based Address Generator for the de-interleaver used in OFDM-WiMAXtransreceiver is proposed. The relationships between various Address LUTs implementing different interleaver / de-interleaver depths within a modulation scheme have been exploited to model the proposed Address Generator. The proposed design shows 81.25% saving of memory blocks in comparison with conventional technique. Hardware structure of the Address Generator is developed and is converted into a VHDL model using Xilinx Integrated Software Environment (ISE). Simulation results obtained using ModelSim XE-III verifies the functionality of the proposed design. Comparative study of FPGA implementation results of the design on two different platforms is presented. Performance improvement of approximately 30% in terms of maximum operating frequency over a recent work is also obtained. 

  • Efficient FPGA Implementation of Address Generator for WiMAX Deinterleaver
    IEEE Transactions on Circuits and Systems II: Express Briefs, 2013
    Co-Authors: Bijoy Kumar Upadhyaya, Salil Kumar Sanyal
    Abstract:

    In this brief, a low-complexity and novel technique is proposed to efficiently implement the Address generation circuitry of the 2-D deinterleaver used in the WiMAX transreceiver using the Xilinx field-programmable gate array (FPGA). The floor function associated with the implementation of the steps, required for the permutation of the incoming bit stream in channel interleaver/deinterleaver for IEEE 802.16e standard is very difficult to implement in FPGA. A simple algorithm along with its mathematical background developed in this brief, eliminates the requirement of floor function and thereby allows low-complexity FPGA implementation. The use of an internal multiplier of FPGA and the sharing of resources for quadrature phase-shift keying, 16-quadrature-amplitude modumodulation (QAM), and 64-QAM modulations along with all possible code rates makes our approach to be novel and highly efficient when compared with conventional look-up table-based approach. The proposed approach exhibits significant improvement in the use of FPGA resources. Exhaustive simulation has been carried out to claim supremacy of our proposed work.

  • An Improved LUT Based Reconfigurable Multimode Interleaver for WLAN Application
    , 2011
    Co-Authors: Bijoy Kumar Upadhyaya, Salil Kumar Sanyal
    Abstract:

    IEEE 802.11 based wireless LAN is considered to be the most prevailing broadband indoor networking technology. Fast spread of wireless data communication systems and the ever increasing demand for faster data rates require quick design, implementation and test of new wireless algorithms for data communications. In this paper we present an improved technique to model the multimode interleaver used in IEEE 802.11a and IEEE 802.11g based WLAN in VHDL using Xilinx ISE. Our proposed technique has look up table based Address Generator and FPGA’s embedded resource based optimized memory. This technique provides higher operating frequency and better FPGA resource utilization compared to available work so far. Use of FPGA’s embedded memory offers advantages like reduced access time, lesser occupancy of circuit board and lower power consumption than external memory based techniques. The look up tables of the Address Generator is also modeled using FPGA’s embedded memory and thereby making the design more efficient in terms of FPGA resource utilization. Comparative analysis of our proposed work with presently available works in literature has been made in respect of the use of FPGA’s internal resources, maximum operating frequency and power consumption. The simulation result obtained using ModelSim XE-III software is also presented.

Liang-gee Chen – One of the best experts on this subject based on the ideXlab platform.

  • Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems
    Journal of VLSI signal processing systems for signal image and video technology, 2005
    Co-Authors: Po-chih Tseng, Chao-tsung Huang, Liang-gee Chen
    Abstract:

    In this paper, a novel reconfigurable discrete wavewaveletnsform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable Address Generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable Address Generator handles flexible Address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.

  • Reconfigurable discrete wavelet transform architecture for advanced multimedia systems
    2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682), 1
    Co-Authors: Po-chih Tseng, Chao-tsung Huang, Liang-gee Chen
    Abstract:

    A novel reconfigurable discrete wavewaveletnsform architecture is proposed to meet the diverse computing requirements of advanced multimedia systems. The proposed architecture mainly consists of a reconfigurable processing element array and a reconfigurable Address Generator, featuring a dynamically reconfigurable capability where the wavelet filter kernels and wavelet decomposition structures can be reconfigured at run-time with little overhead. The lifting-based reconfigurable processing element array possesses better computational efficiency than a convolution-based architecture, and a systematic design method is provided to generate the hardware configurations of different wavelet filter kernels for it. The reconfigurable Address Generator handles flexible Address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by the TSMC 0.35 /spl mu/m 1P4M CMOS process, and, at 50 MHz, it can achieve at most 100 Mpixel/sec transform throughput, proving it to be a universal and extremely flexible computing engine for advanced multimedia systems.