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Algorithm Designer

The Experts below are selected from a list of 186 Experts worldwide ranked by ideXlab platform

P. Banerjee – 1st expert on this subject based on the ideXlab platform

  • An Algorithm for trading off quantization error with hardware resources for MATLAB-based FPGA design
    IEEE Transactions on Computers, 2005
    Co-Authors: P. Banerjee

    Abstract:

    Most practical FPGA designs of digital signal processing (DSP) applications are limited to fixed-point arithmetic owing to the cost and complexity of floating-point hardware. While mapping DSP applications onto FPGAs, a DSP Algorithm Designer must determine the dynamic range and desired precision of input, intermediate, and output signals in a design implementation. The first step in a MATLAB-based hardware design flow is the conversion of the floating-point MATLAB code into a fixed-point version using “quantizers” from the filter design and analysis (FDA) toolbox for MATLAB. This paper describes an approach to automate the conversion of floating-point MATLAB programs into fixed-point MATLAB programs, for mapping to FPGAs by profiling the expected inputs to estimate errors. Our Algorithm attempts to minimize the hardware resources while constraining the quantization error within a specified limit. Experimental results on five MATLAB benchmarks are reported for Xilinx Virtex II FPGAs.

  • An Algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design
    Proceedings. 41st Design Automation Conference 2004., 2004
    Co-Authors: P. Banerjee

    Abstract:

    Most practical FPGA designs of digital signal processing applications are limited to fixed-point arithmetic owing to the cost and complexiry of floating-point hardware. While mapping DSP applications onto FPGAs, a DSP Algorithm Designer, who often develops his applications in MATLAB, must determine the dynamic range and desired precision of input, intermediate and output signals in a design implementation to ensure that the Algorithm fidelity criteria are met. The first step in a flow to map MATLAB applications into hardware is the conversion of the floating-point MATLAB Algorithm into a fixed-point version. This paper describes an approach to automate this conversion, for mapping to FPGAs by profiling the expected inputs to estimate errors. Our Algorithm attempts to minimize the hardware resources while constraining the quantization error within a specified limit

Viktor K Prasanna – 2nd expert on this subject based on the ideXlab platform

  • an Algorithm Designer s workbench for platform fpgas
    Lecture Notes in Computer Science, 2003
    Co-Authors: Sumit Mohanty, Viktor K Prasanna

    Abstract:

    Growing gate density, availability of embedded multipliers and memory, and integration of traditional processors are some of the key advantages of Platform FPGAs. Such FPGAs are attractive for implementing compute intensive signal processing kernels used in wired as well as wireless mobile devices. However, Algorithm design using Platform FPGAs, with energy dissipation as an additional performance metric for mobile devices, poses significant challenges. In this paper, we propose an Algorithm Designer‘s workbench that addresses the above issues. The workbench supports formal modeling of the signal processing kernels, evaluation of latency, energy, and area of a design, and performance tradeoff analysis to facilitate optimization. The workbench includes a high-level estimator for rapid performance estimation and widely used low-level simulators for detailed simulation. Features include a confidence interval based technique for accurate power estimation and facility to store Algorithm designs as library of models for reuse. We demonstrate the use of the workbench through design of matrix multiplication Algorithm for Xilinx Virtex-II Pro.

Justin L. Tripp – 3rd expert on this subject based on the ideXlab platform

  • An Effective Automatic Memory Allocation Algorithm Based on Schedule Length in a Novel C to FPGA Compiler
    2007 International Conference on Field Programmable Logic and Applications, 2007
    Co-Authors: Kristopher D. Peterson, Justin L. Tripp

    Abstract:

    A significant challenge in designing Algorithms for FPGA-based reconfigurable computers is the exposed, non-cached memory subsystem. In the absence of dedicated hardware to manage a cached memory hierarchy, the Algorithm Designer must explicitly allocate data within a collection of memory banks, and schedule access to the memories in the Algorithm‘s datapaths. The physical location in memory affects the datapath schedule, yet data dependencies in the Algorithm can suggest allocation strategies to increase instruction level parallelism. In this work, we present three Algorithms that automatically allocate arrays to memory banks and schedule datapaths that use those memories. Our Algorithm allows the user to trade-off optimal results versus longer iterative analysis.