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R Castello - One of the best experts on this subject based on the ideXlab platform.

  • analysis and design of a 260 mhz rf bandwidth 22 dbm oob iip3 mixer first receiver with third order current mode filtering tia
    IEEE Journal of Solid-state Circuits, 2020
    Co-Authors: Giacomo Pini, Danilo Manstretta, R Castello
    Abstract:

    The design of a mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for 5G applications below 6 GHz is presented. The transimpedance amplifier immediately following the passive mixer is based on a low-power modified regulated cascode with enhanced selectivity, instead of a conventional shunt-feedback architecture. At the mixer output, thanks to a positive feedback capacitance multiplication, a third-order low-pass filtering in the current domain is performed. A simplified non-linear model is used to demonstrate that, thanks to the improved selectivity, linearity close to the band edge is highly improved. Wide bandwidth, high linearity, and low power are thus achieved. Measurements on a 28-nm CMOS chip prototype show Alternate Channel IIP3, IIP2, and P1 dB of +22, +70, and +3 dBm, respectively. Receiver (RX) noise figure (NF) is 5.5 dB, while power consumption is 21.6 mW (in the signal path) and 7.8 mW/GHz (for local oscillator (LO) generation) with 1.8-/1.2-V supply.

  • a 260 mhz rf bandwidth mixer first receiver with third order current mode filtering tia
    European Solid-State Circuits Conference, 2019
    Co-Authors: Giacomo Pini, Danilo Manstretta, R Castello
    Abstract:

    A mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for the 5G lower frequency band (below 6 GHz) is presented. The filtering trans-impedance amplifier immediately following the mixer is based on a regulated cascode, instead of a conventional shunt-feedback architecture. Thanks to a positive-feedback capacitance multiplication, third-order low-pass filtering in the current domain is performed. Wide bandwidth, high linearity, and low power are thus achieved. Measurements on a 28-nm CMOS chip prototype show Alternate Channel IIP3 and P1dB of +22 dBm and +3 dBm, respectively. RX NF is 5.5 dB while power consumption is 21.6 mW (signal path) and 7.8-mW/GHz (LO) with 1.8/1.2-V supply.

Giacomo Pini - One of the best experts on this subject based on the ideXlab platform.

  • analysis and design of a 260 mhz rf bandwidth 22 dbm oob iip3 mixer first receiver with third order current mode filtering tia
    IEEE Journal of Solid-state Circuits, 2020
    Co-Authors: Giacomo Pini, Danilo Manstretta, R Castello
    Abstract:

    The design of a mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for 5G applications below 6 GHz is presented. The transimpedance amplifier immediately following the passive mixer is based on a low-power modified regulated cascode with enhanced selectivity, instead of a conventional shunt-feedback architecture. At the mixer output, thanks to a positive feedback capacitance multiplication, a third-order low-pass filtering in the current domain is performed. A simplified non-linear model is used to demonstrate that, thanks to the improved selectivity, linearity close to the band edge is highly improved. Wide bandwidth, high linearity, and low power are thus achieved. Measurements on a 28-nm CMOS chip prototype show Alternate Channel IIP3, IIP2, and P1 dB of +22, +70, and +3 dBm, respectively. Receiver (RX) noise figure (NF) is 5.5 dB, while power consumption is 21.6 mW (in the signal path) and 7.8 mW/GHz (for local oscillator (LO) generation) with 1.8-/1.2-V supply.

  • a 260 mhz rf bandwidth mixer first receiver with third order current mode filtering tia
    European Solid-State Circuits Conference, 2019
    Co-Authors: Giacomo Pini, Danilo Manstretta, R Castello
    Abstract:

    A mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for the 5G lower frequency band (below 6 GHz) is presented. The filtering trans-impedance amplifier immediately following the mixer is based on a regulated cascode, instead of a conventional shunt-feedback architecture. Thanks to a positive-feedback capacitance multiplication, third-order low-pass filtering in the current domain is performed. Wide bandwidth, high linearity, and low power are thus achieved. Measurements on a 28-nm CMOS chip prototype show Alternate Channel IIP3 and P1dB of +22 dBm and +3 dBm, respectively. RX NF is 5.5 dB while power consumption is 21.6 mW (signal path) and 7.8-mW/GHz (LO) with 1.8/1.2-V supply.

Danilo Manstretta - One of the best experts on this subject based on the ideXlab platform.

  • analysis and design of a 260 mhz rf bandwidth 22 dbm oob iip3 mixer first receiver with third order current mode filtering tia
    IEEE Journal of Solid-state Circuits, 2020
    Co-Authors: Giacomo Pini, Danilo Manstretta, R Castello
    Abstract:

    The design of a mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for 5G applications below 6 GHz is presented. The transimpedance amplifier immediately following the passive mixer is based on a low-power modified regulated cascode with enhanced selectivity, instead of a conventional shunt-feedback architecture. At the mixer output, thanks to a positive feedback capacitance multiplication, a third-order low-pass filtering in the current domain is performed. A simplified non-linear model is used to demonstrate that, thanks to the improved selectivity, linearity close to the band edge is highly improved. Wide bandwidth, high linearity, and low power are thus achieved. Measurements on a 28-nm CMOS chip prototype show Alternate Channel IIP3, IIP2, and P1 dB of +22, +70, and +3 dBm, respectively. Receiver (RX) noise figure (NF) is 5.5 dB, while power consumption is 21.6 mW (in the signal path) and 7.8 mW/GHz (for local oscillator (LO) generation) with 1.8-/1.2-V supply.

  • a 260 mhz rf bandwidth mixer first receiver with third order current mode filtering tia
    European Solid-State Circuits Conference, 2019
    Co-Authors: Giacomo Pini, Danilo Manstretta, R Castello
    Abstract:

    A mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for the 5G lower frequency band (below 6 GHz) is presented. The filtering trans-impedance amplifier immediately following the mixer is based on a regulated cascode, instead of a conventional shunt-feedback architecture. Thanks to a positive-feedback capacitance multiplication, third-order low-pass filtering in the current domain is performed. Wide bandwidth, high linearity, and low power are thus achieved. Measurements on a 28-nm CMOS chip prototype show Alternate Channel IIP3 and P1dB of +22 dBm and +3 dBm, respectively. RX NF is 5.5 dB while power consumption is 21.6 mW (signal path) and 7.8-mW/GHz (LO) with 1.8/1.2-V supply.

J S Kenney - One of the best experts on this subject based on the ideXlab platform.

  • a low voltage w cdma polar transmitter with digital envelope path gain compensation
    IEEE Microwave and Wireless Components Letters, 2006
    Co-Authors: Jauhorng Chen, P Fedorenko, J S Kenney
    Abstract:

    This letter presents a polar transmitter using a dual-phase pulsewidth-modulated buck converter with a 50-MHz effective switching frequency. Using a wideband code division multiple access voice signal, the overall system can achieve 52.8% drain efficiency (49.8% power added efficiency) at 24-dBm output power at 836.5MHz with a 3.5-V supply voltage, while passing both adjacent Channel leakage power ratio (ACLR1) and Alternate Channel leakage power (ACLR2) specifications. A digital finite impulse response filter is included in the envelope path to compensate for gain roll-off at higher baseband frequencies. This envelope path compensation allows greater linear bandwidth to be achieved at lower switching frequencies, thus boosting efficiency, and improving ACLR by as much as 8dB. The polar transmitter is characterized over a supply voltage of 2.5-4.5V, making it well suited for battery powered, handheld applications

  • Power amplifier linearization with digital pre-distortion and crest factor reduction
    2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535), 2004
    Co-Authors: R. Sperlich, Y. Park, G. Copeland, J S Kenney
    Abstract:

    This paper investigates the use of crest factor reduction (CFR) as a cost-effective method of increasing output power and efficiency for power amplifiers (PAs) operating in conjunction with pre-distortion linearization system. Previous result indicated adjacent and Alternate Channel leakage ratio (ACLR) improvements of 10-12 dB were obtained from memoryless pre-distortion of a high power amplifier using a standard IS-95 signal with a peak-to-average ratio of approximately 9.6 dB. This paper investigates the effect of using CFR data in conjunction with the same digital pre-distortion platform. It was found that using CFR with pre-distortion allows for an increase of 2.7 dB in output power while maintaining the same ACLR of -45 dBc at 885 KHz offset on a 30W LDMOS PA. Furthermore, due to the decreased output back-off an effective efficiency improvement of 5.6% was also realized.

Jauhorng Chen - One of the best experts on this subject based on the ideXlab platform.

  • a multi level pulse modulated polar transmitter using digital pulse width modulation
    IEEE Microwave and Wireless Components Letters, 2010
    Co-Authors: Jauhorng Chen, Haoshun Yang, Yijan Emery Chen
    Abstract:

    This letter presents a multi-level pulse modulated polar transmitter architecture. Compared to a conventional gate-modulated envelope elimination and restoration transmitter, the use of the proposed technique is capable of reducing the in-band quantization noise level. Moreover, the proposed technique can increase the pulse-width modulation sampling frequency by relaxing its resolution requirement, which eases the filtering requirement at the output. A prototype transmitter system is constructed using commercially available components. Using a CDMA2000 1X signal at 836.5 MHz, it achieved over 40% power-added efficiency at 24.5 dBm output power level while passing the adjacent and Alternate Channel power ratios for the CDMA2000 standard.

  • a low voltage w cdma polar transmitter with digital envelope path gain compensation
    IEEE Microwave and Wireless Components Letters, 2006
    Co-Authors: Jauhorng Chen, P Fedorenko, J S Kenney
    Abstract:

    This letter presents a polar transmitter using a dual-phase pulsewidth-modulated buck converter with a 50-MHz effective switching frequency. Using a wideband code division multiple access voice signal, the overall system can achieve 52.8% drain efficiency (49.8% power added efficiency) at 24-dBm output power at 836.5MHz with a 3.5-V supply voltage, while passing both adjacent Channel leakage power ratio (ACLR1) and Alternate Channel leakage power (ACLR2) specifications. A digital finite impulse response filter is included in the envelope path to compensate for gain roll-off at higher baseband frequencies. This envelope path compensation allows greater linear bandwidth to be achieved at lower switching frequencies, thus boosting efficiency, and improving ACLR by as much as 8dB. The polar transmitter is characterized over a supply voltage of 2.5-4.5V, making it well suited for battery powered, handheld applications