The Experts below are selected from a list of 297 Experts worldwide ranked by ideXlab platform

Sergio Bampi - One of the best experts on this subject based on the ideXlab platform.

  • A Digitally Reconfigurable Sensor Interface for SOC using Delta-Sigma Modulators
    2006 IEEE Instrumentation and Measurement Technology Conference Proceedings, 2006
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    Many systems on chip (SOC) applications require a mixed signal (Analog and digital blocks) design approach. The incorporation of some degree of Analog programmability in current digital reconfigurable devices is desired, so the same processor platform can be used in different applications. As mixed signal SOC applications deal with heterogeneous signals (low and high frequency) and signal processing functions (linear and non-linear), the ideal Analog Interface architecture should be able to manage this heterogeneity. In this paper we propose the use of a constant Analog architecture for the SOC Analog Interface, able to deliver constant performance in this heterogeneous environment. The proposed approach is based on a set composed by a mixer and a band-pass SigmaDelta modulator. Several linear and nonlinear applications can be mapped over the proposed Interface architecture for processing Analog input signals ranging from low to high frequency. A prototype was built and characterized. Practical results show constant and predictable performance over a large frequency range of the input signal. The achieved results also support the Interface potential use for general Analog interfacing and programmable signal processing

  • an Analog signal Interface with constant performance for socs
    International Symposium on Circuits and Systems, 2003
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    This paper describes a new architecture for programmable Analog Interface circuits. One of the main consequences of Analog programmability is the performance penalty introduced by this feature. The proposed new architecture attenuates the programmability penalty and, even more important, it provides constant performance over a wide range of input signal band. Using a mixer inside the proposed architecture, we propose an Analog programmable Interface that can process signals from DC to high frequencies with constant performance, overcoming the need to change the architecture as a function of the target domain application. This paper presents the mathematical framework and experimental results showing the proposed architecture applied to linear filter design over a large frequency range.

  • SBCCI - A universal high-performance Analog Interface for signal processing SOCs
    16th Symposium on Integrated Circuits and Systems Design 2003. SBCCI 2003. Proceedings., 1
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    Integrated circuit technology evolution boosts the development of system-on-a-chip (SOC) applications. These applications usually integrate digital blocks and may, for extended functionality, include also Analog Interface circuits in the same die. However, the evolution of design automation tools from system specification to implementation of digital systems has reached a much higher level of maturity than their Analog counterparts. This lower degree of automation of the Analog subsystem has become a bottleneck in the development of complete systems. In spite of the past efforts to develop Analog design automation tools, the general solution for the Analog part synthesis has not been found. In this work, we propose a new look at the design problem, by the use of a universal Analog architecture for the SOC Analog Interface. Moreover, the proposed architecture leads to programmable Analog processing within the digital modules domain. Several linear and nonlinear applications can be mapped over the proposed Interface architecture. A prototype was built and some measurements results are shown to support the potential for universal interfacing and programmable Analog processing. Practical results show constant performance over a large frequency range of the input signal. Some guidelines are addressed on how the proposed architecture can lead to greater level of Analog design automation.

  • ISCAS - Reconfigurable Analog Interface for mixed signal SOC
    2006 IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    This work discusses the development, modeling and implementation results of a programmable architecture to be employed for Analog signals interfacing in mixed-signal SOC. The proposed architecture is able to achieve wide frequency range, covering a large range of applications with constant performance, allied to digital configuration compatibility. The proposed approach utilizes the concept of frequency translation (mixing) and /spl Sigma//spl Delta/ modulation leading to a fairly constant Analog block for an input signal uniform treatment from DC to high frequencies. The Interface performance theoretical model is addressed for supporting the design space exploration and also the physical design. An Interface prototype using a fourth order continuous time band-pass /spl Sigma//spl Delta/ modulator is built and characterized validating the proposed performance model. The usage of this Interface as a multi-band parametric ADC is presented.

Eric Fabris - One of the best experts on this subject based on the ideXlab platform.

  • A Digitally Reconfigurable Sensor Interface for SOC using Delta-Sigma Modulators
    2006 IEEE Instrumentation and Measurement Technology Conference Proceedings, 2006
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    Many systems on chip (SOC) applications require a mixed signal (Analog and digital blocks) design approach. The incorporation of some degree of Analog programmability in current digital reconfigurable devices is desired, so the same processor platform can be used in different applications. As mixed signal SOC applications deal with heterogeneous signals (low and high frequency) and signal processing functions (linear and non-linear), the ideal Analog Interface architecture should be able to manage this heterogeneity. In this paper we propose the use of a constant Analog architecture for the SOC Analog Interface, able to deliver constant performance in this heterogeneous environment. The proposed approach is based on a set composed by a mixer and a band-pass SigmaDelta modulator. Several linear and nonlinear applications can be mapped over the proposed Interface architecture for processing Analog input signals ranging from low to high frequency. A prototype was built and characterized. Practical results show constant and predictable performance over a large frequency range of the input signal. The achieved results also support the Interface potential use for general Analog interfacing and programmable signal processing

  • an Analog signal Interface with constant performance for socs
    International Symposium on Circuits and Systems, 2003
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    This paper describes a new architecture for programmable Analog Interface circuits. One of the main consequences of Analog programmability is the performance penalty introduced by this feature. The proposed new architecture attenuates the programmability penalty and, even more important, it provides constant performance over a wide range of input signal band. Using a mixer inside the proposed architecture, we propose an Analog programmable Interface that can process signals from DC to high frequencies with constant performance, overcoming the need to change the architecture as a function of the target domain application. This paper presents the mathematical framework and experimental results showing the proposed architecture applied to linear filter design over a large frequency range.

  • SBCCI - A universal high-performance Analog Interface for signal processing SOCs
    16th Symposium on Integrated Circuits and Systems Design 2003. SBCCI 2003. Proceedings., 1
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    Integrated circuit technology evolution boosts the development of system-on-a-chip (SOC) applications. These applications usually integrate digital blocks and may, for extended functionality, include also Analog Interface circuits in the same die. However, the evolution of design automation tools from system specification to implementation of digital systems has reached a much higher level of maturity than their Analog counterparts. This lower degree of automation of the Analog subsystem has become a bottleneck in the development of complete systems. In spite of the past efforts to develop Analog design automation tools, the general solution for the Analog part synthesis has not been found. In this work, we propose a new look at the design problem, by the use of a universal Analog architecture for the SOC Analog Interface. Moreover, the proposed architecture leads to programmable Analog processing within the digital modules domain. Several linear and nonlinear applications can be mapped over the proposed Interface architecture. A prototype was built and some measurements results are shown to support the potential for universal interfacing and programmable Analog processing. Practical results show constant performance over a large frequency range of the input signal. Some guidelines are addressed on how the proposed architecture can lead to greater level of Analog design automation.

  • ISCAS - Reconfigurable Analog Interface for mixed signal SOC
    2006 IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    This work discusses the development, modeling and implementation results of a programmable architecture to be employed for Analog signals interfacing in mixed-signal SOC. The proposed architecture is able to achieve wide frequency range, covering a large range of applications with constant performance, allied to digital configuration compatibility. The proposed approach utilizes the concept of frequency translation (mixing) and /spl Sigma//spl Delta/ modulation leading to a fairly constant Analog block for an input signal uniform treatment from DC to high frequencies. The Interface performance theoretical model is addressed for supporting the design space exploration and also the physical design. An Interface prototype using a fourth order continuous time band-pass /spl Sigma//spl Delta/ modulator is built and characterized validating the proposed performance model. The usage of this Interface as a multi-band parametric ADC is presented.

D. Martinez - One of the best experts on this subject based on the ideXlab platform.

  • beam profile wire scanner halo scraper sensor Analog Interface electronics
    PACS2001. Proceedings of the 2001 Particle Accelerator Conference (Cat. No.01CH37268), 2001
    Co-Authors: M. Gruchalla, D. Barr, T. Cote, L.a. Day, D. Gilpatrick, M. Stettler, J F Ohara, D. Martinez
    Abstract:

    The halo experiment presently being conducted at the Low Energy Demonstration Accelerator (LEDA) at Los Alamos National Laboratory utilizes a generally traditional wire scanner for measurement of the beam core profile and a graphite scraper for measurement of the tails of the beam distribution. A lossy integrator is used to detect the replacement charge flowing to the wire and scraper. Independent programmable dc-bias voltages are applied to the wire and the scraper through the Analog electronic Interface to optimize the charge capture from the two sensors. A programmable guard voltage is applied to isolate the scraper from the resistivity of the cooling system. A programmable gain provides a total dynamic range in the Analog electronics of greater than about one part in 10/sup 6/. The Analog signal is digitized to 14 bits plus sign, and the equivalent input noise is nominally 30 fC.

  • Beam profile wire-scanner/halo-scraper sensor Analog Interface electronics
    PACS2001. Proceedings of the 2001 Particle Accelerator Conference (Cat. No.01CH37268), 1
    Co-Authors: M. Gruchalla, J.f. O'hara, D. Barr, T. Cote, L.a. Day, D. Gilpatrick, M. Stettler, D. Martinez
    Abstract:

    The halo experiment presently being conducted at the Low Energy Demonstration Accelerator (LEDA) at Los Alamos National Laboratory utilizes a generally traditional wire scanner for measurement of the beam core profile and a graphite scraper for measurement of the tails of the beam distribution. A lossy integrator is used to detect the replacement charge flowing to the wire and scraper. Independent programmable dc-bias voltages are applied to the wire and the scraper through the Analog electronic Interface to optimize the charge capture from the two sensors. A programmable guard voltage is applied to isolate the scraper from the resistivity of the cooling system. A programmable gain provides a total dynamic range in the Analog electronics of greater than about one part in 10/sup 6/. The Analog signal is digitized to 14 bits plus sign, and the equivalent input noise is nominally 30 fC.

Minkyu Song - One of the best experts on this subject based on the ideXlab platform.

  • an 8 bit 200 msps cmos a d converter for Analog Interface module of tft lcd driver
    International Symposium on Circuits and Systems, 2001
    Co-Authors: Samgsuk Kim, Minkyu Song
    Abstract:

    A 3 V 8-bit 200 MSPS CMOS folding/interpolation A/D converter for Analog Interface module of TFT-LCD Driver is proposed. It is composed of both a coarse ADC and a fine ADC whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (interpolation Rate) is 8, respectively. For the purpose of improving SNDR, distributed track-and-hold circuits are included at the input stage. In order to obtain a high speed operation and low power consumption, further, a novel Analog latch and digital encoder based on a fast compression algorithm are proposed. The chip has been fabricated with a 0.35 /spl mu/m 2-poly 3-metal CMOS technology. The effective chip area is about 1.2 mm/spl times/0.8 mm and it dissipates about 210 mW at 3 V power supply. The INL and DNL are within 1 LSB, respectively. The SNDR is about 43 dB, when the input frequency reaches 10 MHz at 200 MHz clock frequency.

  • ISCAS (1) - An 8-bit 200 MSPS CMOS A/D converter for Analog Interface module of TFT-LCD driver
    ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 1
    Co-Authors: Samgsuk Kim, Minkyu Song
    Abstract:

    A 3 V 8-bit 200 MSPS CMOS folding/interpolation A/D converter for Analog Interface module of TFT-LCD Driver is proposed. It is composed of both a coarse ADC and a fine ADC whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (interpolation Rate) is 8, respectively. For the purpose of improving SNDR, distributed track-and-hold circuits are included at the input stage. In order to obtain a high speed operation and low power consumption, further, a novel Analog latch and digital encoder based on a fast compression algorithm are proposed. The chip has been fabricated with a 0.35 /spl mu/m 2-poly 3-metal CMOS technology. The effective chip area is about 1.2 mm/spl times/0.8 mm and it dissipates about 210 mW at 3 V power supply. The INL and DNL are within 1 LSB, respectively. The SNDR is about 43 dB, when the input frequency reaches 10 MHz at 200 MHz clock frequency.

Luigi Carro - One of the best experts on this subject based on the ideXlab platform.

  • A Digitally Reconfigurable Sensor Interface for SOC using Delta-Sigma Modulators
    2006 IEEE Instrumentation and Measurement Technology Conference Proceedings, 2006
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    Many systems on chip (SOC) applications require a mixed signal (Analog and digital blocks) design approach. The incorporation of some degree of Analog programmability in current digital reconfigurable devices is desired, so the same processor platform can be used in different applications. As mixed signal SOC applications deal with heterogeneous signals (low and high frequency) and signal processing functions (linear and non-linear), the ideal Analog Interface architecture should be able to manage this heterogeneity. In this paper we propose the use of a constant Analog architecture for the SOC Analog Interface, able to deliver constant performance in this heterogeneous environment. The proposed approach is based on a set composed by a mixer and a band-pass SigmaDelta modulator. Several linear and nonlinear applications can be mapped over the proposed Interface architecture for processing Analog input signals ranging from low to high frequency. A prototype was built and characterized. Practical results show constant and predictable performance over a large frequency range of the input signal. The achieved results also support the Interface potential use for general Analog interfacing and programmable signal processing

  • an Analog signal Interface with constant performance for socs
    International Symposium on Circuits and Systems, 2003
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    This paper describes a new architecture for programmable Analog Interface circuits. One of the main consequences of Analog programmability is the performance penalty introduced by this feature. The proposed new architecture attenuates the programmability penalty and, even more important, it provides constant performance over a wide range of input signal band. Using a mixer inside the proposed architecture, we propose an Analog programmable Interface that can process signals from DC to high frequencies with constant performance, overcoming the need to change the architecture as a function of the target domain application. This paper presents the mathematical framework and experimental results showing the proposed architecture applied to linear filter design over a large frequency range.

  • SBCCI - A universal high-performance Analog Interface for signal processing SOCs
    16th Symposium on Integrated Circuits and Systems Design 2003. SBCCI 2003. Proceedings., 1
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    Integrated circuit technology evolution boosts the development of system-on-a-chip (SOC) applications. These applications usually integrate digital blocks and may, for extended functionality, include also Analog Interface circuits in the same die. However, the evolution of design automation tools from system specification to implementation of digital systems has reached a much higher level of maturity than their Analog counterparts. This lower degree of automation of the Analog subsystem has become a bottleneck in the development of complete systems. In spite of the past efforts to develop Analog design automation tools, the general solution for the Analog part synthesis has not been found. In this work, we propose a new look at the design problem, by the use of a universal Analog architecture for the SOC Analog Interface. Moreover, the proposed architecture leads to programmable Analog processing within the digital modules domain. Several linear and nonlinear applications can be mapped over the proposed Interface architecture. A prototype was built and some measurements results are shown to support the potential for universal interfacing and programmable Analog processing. Practical results show constant performance over a large frequency range of the input signal. Some guidelines are addressed on how the proposed architecture can lead to greater level of Analog design automation.

  • ISCAS - Reconfigurable Analog Interface for mixed signal SOC
    2006 IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: Eric Fabris, Luigi Carro, Sergio Bampi
    Abstract:

    This work discusses the development, modeling and implementation results of a programmable architecture to be employed for Analog signals interfacing in mixed-signal SOC. The proposed architecture is able to achieve wide frequency range, covering a large range of applications with constant performance, allied to digital configuration compatibility. The proposed approach utilizes the concept of frequency translation (mixing) and /spl Sigma//spl Delta/ modulation leading to a fairly constant Analog block for an input signal uniform treatment from DC to high frequencies. The Interface performance theoretical model is addressed for supporting the design space exploration and also the physical design. An Interface prototype using a fourth order continuous time band-pass /spl Sigma//spl Delta/ modulator is built and characterized validating the proposed performance model. The usage of this Interface as a multi-band parametric ADC is presented.