# Analog Voltage

The Experts below are selected from a list of 27399 Experts worldwide ranked by ideXlab platform

### William H Owen – One of the best experts on this subject based on the ideXlab platform.

• ##### a very high precision 500 na cmos floating gate AnalogVoltage reference
IEEE Journal of Solid-state Circuits, 2005
Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H Owen

Abstract:

A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.

• ##### a very high precision 500 na cmos floating gate AnalogVoltage reference
IEEE Journal of Solid-state Circuits, 2005
Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H Owen

Abstract:

A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.

• ##### a very high precision 500 na cmos floating gate AnalogVoltage reference
International Solid-State Circuits Conference, 2005
Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H Owen

Abstract:

A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.

### Bhupendra K Ahuja – One of the best experts on this subject based on the ideXlab platform.

• ##### a very high precision 500 na cmos floating gate AnalogVoltage reference
IEEE Journal of Solid-state Circuits, 2005
Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H Owen

Abstract:

A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.

• ##### a very high precision 500 na cmos floating gate AnalogVoltage reference
IEEE Journal of Solid-state Circuits, 2005
Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H Owen

Abstract:

A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.

• ##### a very high precision 500 na cmos floating gate AnalogVoltage reference
International Solid-State Circuits Conference, 2005
Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H Owen

Abstract:

A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.

### Jiann-jong Chen – One of the best experts on this subject based on the ideXlab platform.

• ##### A Sub-1-μs Ultrafast-Response Buck Converter With Improved Analog–Voltage-Dynamic-Estimation Techniques
IEEE Transactions on Industrial Electronics, 2018
Co-Authors: Jiann-jong Chen, Yuh-shyan Hwang, Hao-hung Chai

Abstract:

A sub-1-μs ultrafast-response buck converter utilizing improved AnalogVoltage-dynamic-estimation (AVDE) techniques is proposed in this letter to improve previous works. First, the improved AVDE controller uses a new pseudocurrent circuit and a new ramp generator to get low gain, wide bandwidth, wide dynamic range, and low equivalent series resistor $(R_{{\text{ESR}}})$ . Second, the proposed converter has high performance, fast transient response, and low output Voltage ripple. Third, the circuit does not need slope compensation so that it is very simple to implement. The switching frequency of the proposed buck converter is 1 MHz for nominal 3.3-V input and 0.8–2.5-V output range application. The experimental results prove that the proposed scheme improves the transient response within 1.2 μs and its maximum power efficiency can be up to 91.9%. The fastest transient time of the proposed converter is only 0.8 μs as the switching frequency is equal to 1 MHz. The settling time of the proposed converter is only within 0.8 cycle of the switching frequency. The maximum load current is 300 mA. The proposed buck converter has been fabricated with a commercial 0.35-μm CMOS 2P4M process, and the total chip area is about ${1.46 \;\text{mm}\times 1.5}$  mm, including PADs.

• ##### A High-Efficiency Fast-Transient-Response Buck Converter with Analog–Voltage-Dynamic-Estimation Techniques
IEEE Transactions on Power Electronics, 2015
Co-Authors: Yuh-shyan Hwang, An Liu, Yuan-bo Chang, Jiann-jong Chen

Abstract:

A fast-transient-response buck converter utilizing AnalogVoltage-dynamic-estimation (AVDE) techniques is proposed in this paper. The responses of the proposed buck converter are very fast when load changes between heavy load and light load. The switching frequency of the proposed buck converter is 1 MHz for nominal 3.3 V input and 1.0-2.5 V output range application. Experimental results prove that the proposed scheme improves the transient response to within 2 μs and that its maximum power efficiency can be up to 95%. The maximum load current is 300 mA. The proposed AVDE buck converter has been fabricated with a commercial 0.35 μm CMOS 2P4M process, the total chip area is about 1.5 mm × 1.5 mm, including PADs.