The Experts below are selected from a list of 27399 Experts worldwide ranked by ideXlab platform
William H Owen - One of the best experts on this subject based on the ideXlab platform.
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a very high precision 500 na cmos floating gate Analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high precision 500 na cmos floating gate Analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high precision 500 na cmos floating gate Analog Voltage reference
International Solid-State Circuits Conference, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high précision 500-nA CMOS floating-gate Analog Voltage reference
2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high precision 500-nA CMOS floating-gate Analog Voltage reference
IEEE Journal of Solid-State Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC)
Bhupendra K Ahuja - One of the best experts on this subject based on the ideXlab platform.
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a very high precision 500 na cmos floating gate Analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high precision 500 na cmos floating gate Analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high precision 500 na cmos floating gate Analog Voltage reference
International Solid-State Circuits Conference, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high précision 500-nA CMOS floating-gate Analog Voltage reference
2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high precision 500-nA CMOS floating-gate Analog Voltage reference
IEEE Journal of Solid-State Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC)
Jiann-jong Chen - One of the best experts on this subject based on the ideXlab platform.
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A Sub-1-μs Ultrafast-Response Buck Converter With Improved Analog-Voltage-Dynamic-Estimation Techniques
IEEE Transactions on Industrial Electronics, 2018Co-Authors: Jiann-jong Chen, Yuh-shyan Hwang, Hao-hung ChaiAbstract:A sub-1-μs ultrafast-response buck converter utilizing improved Analog-Voltage-dynamic-estimation (AVDE) techniques is proposed in this letter to improve previous works. First, the improved AVDE controller uses a new pseudocurrent circuit and a new ramp generator to get low gain, wide bandwidth, wide dynamic range, and low equivalent series resistor $(R_{{\text{ESR}}})$ . Second, the proposed converter has high performance, fast transient response, and low output Voltage ripple. Third, the circuit does not need slope compensation so that it is very simple to implement. The switching frequency of the proposed buck converter is 1 MHz for nominal 3.3-V input and 0.8–2.5-V output range application. The experimental results prove that the proposed scheme improves the transient response within 1.2 μs and its maximum power efficiency can be up to 91.9%. The fastest transient time of the proposed converter is only 0.8 μs as the switching frequency is equal to 1 MHz. The settling time of the proposed converter is only within 0.8 cycle of the switching frequency. The maximum load current is 300 mA. The proposed buck converter has been fabricated with a commercial 0.35-μm CMOS 2P4M process, and the total chip area is about ${1.46 \;\text{mm}\times 1.5}$ mm, including PADs.
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A High-Efficiency Fast-Transient-Response Buck Converter with Analog-Voltage-Dynamic-Estimation Techniques
IEEE Transactions on Power Electronics, 2015Co-Authors: Yuh-shyan Hwang, An Liu, Yuan-bo Chang, Jiann-jong ChenAbstract:A fast-transient-response buck converter utilizing Analog-Voltage-dynamic-estimation (AVDE) techniques is proposed in this paper. The responses of the proposed buck converter are very fast when load changes between heavy load and light load. The switching frequency of the proposed buck converter is 1 MHz for nominal 3.3 V input and 1.0-2.5 V output range application. Experimental results prove that the proposed scheme improves the transient response to within 2 μs and that its maximum power efficiency can be up to 95%. The maximum load current is 300 mA. The proposed AVDE buck converter has been fabricated with a commercial 0.35 μm CMOS 2P4M process, the total chip area is about 1.5 mm × 1.5 mm, including PADs.
Carlos Laber - One of the best experts on this subject based on the ideXlab platform.
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a very high precision 500 na cmos floating gate Analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high precision 500 na cmos floating gate Analog Voltage reference
IEEE Journal of Solid-state Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) <1 ppm//spl deg/C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 /spl mu/V of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm//spl radic/1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-/spl mu/m E/sup 2/PROM CMOS technology.
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a very high precision 500 na cmos floating gate Analog Voltage reference
International Solid-State Circuits Conference, 2005Co-Authors: Bhupendra K Ahuja, Hoa Vu, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high précision 500-nA CMOS floating-gate Analog Voltage reference
2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC) < 1 ppm/°C in CMOS technology. A Fowler-Nordheim tunnel device used as a switch and a poly-poly capacitor form the basis in this reference. Differential dual floating gate architecture helps in achieving extremely low temperature coefficients, and improving power supply rejection. The reference is factory programmed to any value without any trim circuits to within 200 μV of its specified value. The floating-gate Analog Voltage reference (FGAREF) shows a long-term drift of less than 10 ppm/√1000 h. This circuit is ideal for portable and handheld applications with a total current of only 500 nA. This is done by biasing the buffer amplifier in the subthreshold region of operation. It is fabricated using a 25-V 1.5-μm E 2 PROM CMOS technology.
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A very high precision 500-nA CMOS floating-gate Analog Voltage reference
IEEE Journal of Solid-State Circuits, 2005Co-Authors: Bhupendra K Ahuja, Carlos Laber, William H OwenAbstract:A floating gate with stored charge technique has been used to implement a precision Voltage reference achieving a temperature coefficient (TC)
Enrique Berjano - One of the best experts on this subject based on the ideXlab platform.
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Non Volatile and Battery-Less Analog Recording of Physiological Signals Using a Low-Cost Device for Voice Signal Storage: A Feasibility Test
Cardiovascular Engineering and Technology, 2011Co-Authors: Laura Sales-nebot, Enrique BerjanoAbstract:The ChipCorder^® technology employs a non volatile Analog recording technique based on EEPROM technology (i.e. although the signal is time-sampled, its Analog Voltage is stored in memory cells based on capacitors). This technology provides low-cost voice signal storage devices, which use a sampling frequency ( f _s) of ≈6.4 kHz to achieve a storage time ( t _s) of several seconds. Theoretically, reducing f _s should allow a proportional increase in t _s, which could be used to record physiological signals, which have a lower frequency range. However, the manufacturer points out that at certain low sampling frequencies, the Analog Voltage stored in the capacitors could drop to an unacceptable level. For this reason, we designed a feasibility test in order to assess the potential of the ChipCorder^® technology for processing and storing physiological signals. An electrocardiogram signal (ECG) (0.7–100 Hz bandwidth) was recorded and played back using the ISD1210P (Information Storage Devices, CA, USA), reducing f _s from 6.4 kHz to 25 Hz and hence augmenting t _s from 10 to 2526 s. The results showed that the ECG signal was considerably distorted when f _s was lower than 200 Hz ( t _s higher than 320 s). This distortion was due to the aliasing effect, and not to an unacceptable drop in the Analog Voltage stored in the capacitors. These results suggest that the ChipCorder^® technology could be used to design non volatile recording systems for physiological signals of up to several minutes duration, reducing the complexity and cost as compared with systems based on digital techniques.
