The Experts below are selected from a list of 296169 Experts worldwide ranked by ideXlab platform

Benini Luca - One of the best experts on this subject based on the ideXlab platform.

  • Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
    2020
    Co-Authors: Zaruba Florian, Schuiki Fabian, Benini Luca
    Abstract:

    Data-parallel problems, commonly found in data analytics, machine learning, and scientific computing demand ever growing floating-point operations per second under tight area- and energy-efficiency constraints. Application-specific architectures and accelerators, while efficient at a given task, are hard to adjust to algorithmic changes. In this work, we present Manticore, a general-purpose, ultra-efficient, RISC-V, chiplet-based architecture for data-parallel floating-point workloads. We have manufactured a 9$\text{mm}^2$ prototype of the chiplet's computational core in Globalfoundries 22nm FD-SOI process and demonstrate more than 2.5$\times$ improvement in energy efficiency on floating-point intensive workloads compared to high performance compute engines (CPUs and GPUs), despite their more advanced FinFET process. The prototype contains two 64-bit, Application-Class RISC-V Ariane management cores that run a full-fledged Linux OS. The compute capability at high energy and area efficiency is provided by Snitch clusters. Each cluster contains eight small (20kGE) 32-bit integer RISC-V cores, each controlling a large double-precision floating-point unit (120kGE). Each core supports two custom RISC-V ISA extensions: FREP and SSR. The SSR extension elides explicit load and store instructions by encoding them as register reads and writes. The FREP extension mostly decouples the integer core from the FPU by allowing a sequence buffer to issue instructions to the FPU independently. Both extensions allow the tiny, single-issue, integer core to saturate the instruction bandwidth of the FPU and achieve FPU utilization above 90%, with more than 80% of core area dedicated to the FPU.Comment: Hot Chips: A Symposium on High Performance Chips (HC32) 202

  • Prevention of Microarchitectural Covert Channels on an Open-Source 64-bit RISC-V Core
    2020
    Co-Authors: Wistoff Nils, Benini Luca, Schneider Moritz, Gürkaynak, Frank K., Heiser Gernot
    Abstract:

    Covert channels enable information leakage across security boundaries of the operating system. Microarchitectural covert channels exploit changes in execution timing resulting from competing access to limited hardware resources. We use the recent experimental support for time protection, aimed at preventing covert channels, in the seL4 microkernel and evaluate the efficacy of the mechanisms against five known channels on Ariane, an open-source 64-bit Application-Class RISC-V core. We confirm that without hardware support, these defences are expensive and incomplete. We show that the addition of a single-instruction extension to the RISC-V ISA, that flushes microarchitectural state, can enable the OS to close all five evaluated covert channels with low increase in context switch costs and negligible hardware overhead. We conclude that such a mechanism is essential for security.Comment: 6 pages, 7 figures, submitted to CARRV '20, additional appendi

  • The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology
    'Institute of Electrical and Electronics Engineers (IEEE)', 2019
    Co-Authors: Zaruba Florian, Benini Luca
    Abstract:

    The open-source RISC-V ISA is gaining traction, both in industry and academia. The ISA is designed to scale from micro-controllers to server-Class processors. Furthermore, openness promotes the availability of various open-source and commercial implementations. Our main contribution in this work is a thorough power, performance, and efficiency analysis of the RISC-V ISA targeting baseline "Application Class" functionality, i.e. supporting the Linux OS and its Application environment based on our open-source single-issue in-order implementation of the 64 bit ISA variant (RV64GC) called Ariane. Our analysis is based on a detailed power and efficiency analysis of the RISC-V ISA extracted from silicon measurements and calibrated simulation of an Ariane instance (RV64IMC) taped-out in GlobalFoundries 22 FDX technology. Ariane runs at up to 1.7 GHz and achieves up to 40 Gop/sW peak efficiency. We give insight into the interplay between functionality required for Application-Class execution (e.g. virtual memory, caches, multiple modes of privileged operation) and energy cost. Our analysis indicates that ISA heterogeneity and simpler cores with a few critical instruction extensions (e.g. packed SIMD) can significantly boost a RISC-V core's compute energy efficiency.Comment: 11 pages, submitted to IEEE Transaction on Very Large Scale Integration (VLSI) System

Luca Benini - One of the best experts on this subject based on the ideXlab platform.

  • the cost of Application Class processing energy and performance analysis of a linux ready 1 7 ghz 64 bit risc v core in 22 nm fdsoi technology
    IEEE Transactions on Very Large Scale Integration Systems, 2019
    Co-Authors: Florian Zaruba, Luca Benini
    Abstract:

    The open-source RISC-V instruction set architecture (ISA) is gaining traction, both in industry and academia. The ISA is designed to scale from microcontrollers to server-Class processors. Furthermore, openness promotes the availability of various open-source and commercial implementations. Our main contribution in this paper is a thorough power, performance, and efficiency analysis of the RISC-V ISA targeting baseline “Application Class” functionality, i.e., supporting the Linux OS and its Application environment based on our open-source single-issue in-order implementation of the 64-bit ISA variant (RV64GC) called Ariane. Our analysis is based on a detailed power and efficiency analysis of the RISC-V ISA extracted from silicon measurements and calibrated simulation of an Ariane instance (RV64IMC) taped-out in GlobalFoundries 22FDX technology. Ariane runs at up to 1.7-GHz, achieves up to 40-Gop/sW energy efficiency, which is superior to similar cores presented in the literature. We provide insight into the interplay between functionality required for the Application-Class execution (e.g., virtual memory, caches, and multiple modes of privileged operation) and energy cost. We also compare Ariane with RISCY, a simpler and a slower microcontroller-Class core. Our analysis confirms that supporting Application-Class execution implies a nonnegligible energy-efficiency loss and that compute performance is more cost-effectively boosted by instruction extensions (e.g., packed SIMD) rather than the high-frequency operation.

  • A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI
    2019 IFIP IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019
    Co-Authors: Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini
    Abstract:

    The crisis of Moore's law and new dominant Machine Learning workloads require a paradigm shift towards finely tunable-precision (a.k.a. transprecision) computing. More specifically, we need floating-point circuits that are capable to operate on many formats with high flexibility. We present the first silicon implementation of a 64-bit transprecision floating-point unit. It fully supports the standard double, single, and half precision, alongside custom bfloat and 8 bit formats. Operations occur on scalars or 2, 4, or 8-way SIMD vectors. We have integrated the 247 kGE unit into a 64 bit Application-Class RISC-V processor core, where the added transprecision support accounts for an energy and area overhead of merely 11% and 9%, respectively; yet achieving speedups and per-datum energy gains of 7.3x and 7.94x. We implemented the design in a 22 nm FD-SOI technology. The unit achieves energy efficiencies between 75 Gflop/sW and 1.24 Tflop/sW, and a performance between 1.85 Gflop/s and 14.83 Gflop/s, across formats.

Sanjay J Patel - One of the best experts on this subject based on the ideXlab platform.

  • tradeoffs in designing accelerator architectures for visual computing
    International Symposium on Microarchitecture, 2008
    Co-Authors: Aqeel Mahesri, Daniel R Johnson, Neal Crago, Sanjay J Patel
    Abstract:

    Visualization, interaction, and simulation (VIS) constitute a Class of Applications that is growing in importance. This Class includes Applications such as graphics rendering, video encoding, simulation, and computer vision. These Applications are ideally suited for accelerators because of their parallelizability and demand for high throughput. We compile a benchmark suite, VISBench, to serve as a proxy for this Application Class.

  • tradeoffs in designing accelerator architectures for visual computing
    International Symposium on Microarchitecture, 2008
    Co-Authors: Aqeel Mahesri, Daniel R Johnson, Neal Crago, Sanjay J Patel
    Abstract:

    Visualization, interaction, and simulation (VIS) constitute a Class of Applications that is growing in importance. This Class includes Applications such as graphics rendering, video encoding, simulation, and computer vision. These Applications are ideally suited for accelerators because of their parallelizability and demand for high throughput. We compile a benchmark suite, VIS- Bench, to serve as a proxy for this Application Class. We use VISBench to examine some important high level decisions for an accelerator architecture. We propose a highly parallel base architecture. We examine the need for synchronization and data communication. We also examine GPU-style SIMD execution and find that a MIMD architecture usually performs better. Given these high level choices, we use VISBench to explore the microarchitectural design space. We analyze area versus performance tradeoffs in designing individual cores and the memory hierarchy. We find that a design made of small, simple cores achieves much higher throughput than a general purpose uniprocessor. Further, we find that a limited amount of support for ILP within each core aids overall performance. We find that fine-grained multithreading improves performance, but only up to a point. We find that word-level (SSE-style) SIMD provides a poor performance to area ratio. Finally, we find that sufficient memory and cache bandwidth is essential to performance.

Joseph O. Chan - One of the best experts on this subject based on the ideXlab platform.

  • Data Warehousing and Data Mining: A Course in MBA and MSIS Program from Uses Perspective
    2016
    Co-Authors: Shamsul Chowdhury, Joseph O. Chan
    Abstract:

    Over the past years data warehousing and data mining tools have evolved from research into a unique and popular business Application Class for decision support and business intelligence. The paper presents and discusses the main components and contents of a course in data warehousing and data mining offered in the graduate business curriculum of an American university in the Midwest. Further, it also discusses how the course was delivered. The course has been designed from lessons learned in research and practice in the field. Key to the development and success of the course is an on-going collaboration between a large company in the retailing branch and the university. Collaboration with the business world has proven invaluable in building bridges between the academic institution and the real world. However, teaching a course in a dynamic field like this will always remain a challenge

Zaruba Florian - One of the best experts on this subject based on the ideXlab platform.

  • Manticore: A 4096-core RISC-V Chiplet Architecture for Ultra-efficient Floating-point Computing
    2020
    Co-Authors: Zaruba Florian, Schuiki Fabian, Benini Luca
    Abstract:

    Data-parallel problems, commonly found in data analytics, machine learning, and scientific computing demand ever growing floating-point operations per second under tight area- and energy-efficiency constraints. Application-specific architectures and accelerators, while efficient at a given task, are hard to adjust to algorithmic changes. In this work, we present Manticore, a general-purpose, ultra-efficient, RISC-V, chiplet-based architecture for data-parallel floating-point workloads. We have manufactured a 9$\text{mm}^2$ prototype of the chiplet's computational core in Globalfoundries 22nm FD-SOI process and demonstrate more than 2.5$\times$ improvement in energy efficiency on floating-point intensive workloads compared to high performance compute engines (CPUs and GPUs), despite their more advanced FinFET process. The prototype contains two 64-bit, Application-Class RISC-V Ariane management cores that run a full-fledged Linux OS. The compute capability at high energy and area efficiency is provided by Snitch clusters. Each cluster contains eight small (20kGE) 32-bit integer RISC-V cores, each controlling a large double-precision floating-point unit (120kGE). Each core supports two custom RISC-V ISA extensions: FREP and SSR. The SSR extension elides explicit load and store instructions by encoding them as register reads and writes. The FREP extension mostly decouples the integer core from the FPU by allowing a sequence buffer to issue instructions to the FPU independently. Both extensions allow the tiny, single-issue, integer core to saturate the instruction bandwidth of the FPU and achieve FPU utilization above 90%, with more than 80% of core area dedicated to the FPU.Comment: Hot Chips: A Symposium on High Performance Chips (HC32) 202

  • The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-ready 1.7GHz 64bit RISC-V Core in 22nm FDSOI Technology
    'Institute of Electrical and Electronics Engineers (IEEE)', 2019
    Co-Authors: Zaruba Florian, Benini Luca
    Abstract:

    The open-source RISC-V ISA is gaining traction, both in industry and academia. The ISA is designed to scale from micro-controllers to server-Class processors. Furthermore, openness promotes the availability of various open-source and commercial implementations. Our main contribution in this work is a thorough power, performance, and efficiency analysis of the RISC-V ISA targeting baseline "Application Class" functionality, i.e. supporting the Linux OS and its Application environment based on our open-source single-issue in-order implementation of the 64 bit ISA variant (RV64GC) called Ariane. Our analysis is based on a detailed power and efficiency analysis of the RISC-V ISA extracted from silicon measurements and calibrated simulation of an Ariane instance (RV64IMC) taped-out in GlobalFoundries 22 FDX technology. Ariane runs at up to 1.7 GHz and achieves up to 40 Gop/sW peak efficiency. We give insight into the interplay between functionality required for Application-Class execution (e.g. virtual memory, caches, multiple modes of privileged operation) and energy cost. Our analysis indicates that ISA heterogeneity and simpler cores with a few critical instruction extensions (e.g. packed SIMD) can significantly boost a RISC-V core's compute energy efficiency.Comment: 11 pages, submitted to IEEE Transaction on Very Large Scale Integration (VLSI) System