The Experts below are selected from a list of 1404 Experts worldwide ranked by ideXlab platform
Ravishankar K. Iyer - One of the best experts on this subject based on the ideXlab platform.
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Hierarchical simulation approach to accurate fault modeling for system dependability evaluation
IEEE Transactions on Software Engineering, 1999Co-Authors: Zbigniew Kalbarczyk, Ravishankar K. Iyer, G.l. Ries, J.u. Patel, M.s. Lee, Y. XiaoAbstract:This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology, effects of low-level (i.e., transistor or circuit level) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault models are obtained via simulation of the transistor-level effect of a radiation particle penetrating a device. The resulting current bursts constitute the first-level fault dictionary and are used in the circuit-level simulation to determine the impact on circuit latches and flip-flops. The latched outputs constitute the next level fault dictionary in the hierarchy and are applied in conducting fault injection simulation at the chip-level under selected workloads or Application programs. Faults injected at the chip-level result in memory corruptions, which are used to form the next level fault dictionary for the system-level simulation of an Application running on simulated hardware. When an Application Terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The system in this sense can be a single workstation or a network. The simulation method is demonstrated and validated in the case study of Myrinet (a commercial, high-speed network) based network system.
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Hierarchical approach to accurate fault modeling for system evaluation
Proceedings. IEEE International Computer Performance and Dependability Symposium. IPDS'98 (Cat. No.98TB100248), 1Co-Authors: Zbigniew Kalbarczyk, G.l. Ries, J.u. Patel, M.s. Lee, Y. Xiao, Ravishankar K. IyerAbstract:This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology effects of low-level (i.e., transistor or circuit levels) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault model is obtained via simulation of the transistor-level effect of a radiation particle penetrating the device. The resulting current burst is used as a fault model in the circuit-level simulation and is injected into the nodes of a circuit/subcircuit. The latched outputs are collected in a fault dictionary and applied in conducting fault injection at the chip level under a selected workload. Faults injected at the chip level result in memory corruption, which is used as a fault model in the system-level simulation. When an Application Terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The simulation method is demonstrated and validated in the case study of Myrinet, a commercial, high-speed network. The study shows that the proposed approach offers a high confidence in the evaluation results, as the system is analyzed in presence of realistic fault conditions. It also demonstrates that the conducted analysis can be used to improve system dependability by identifying recovery mechanisms for failures observed during the experiments.
Y. Xiao - One of the best experts on this subject based on the ideXlab platform.
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Hierarchical simulation approach to accurate fault modeling for system dependability evaluation
IEEE Transactions on Software Engineering, 1999Co-Authors: Zbigniew Kalbarczyk, Ravishankar K. Iyer, G.l. Ries, J.u. Patel, M.s. Lee, Y. XiaoAbstract:This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology, effects of low-level (i.e., transistor or circuit level) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault models are obtained via simulation of the transistor-level effect of a radiation particle penetrating a device. The resulting current bursts constitute the first-level fault dictionary and are used in the circuit-level simulation to determine the impact on circuit latches and flip-flops. The latched outputs constitute the next level fault dictionary in the hierarchy and are applied in conducting fault injection simulation at the chip-level under selected workloads or Application programs. Faults injected at the chip-level result in memory corruptions, which are used to form the next level fault dictionary for the system-level simulation of an Application running on simulated hardware. When an Application Terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The system in this sense can be a single workstation or a network. The simulation method is demonstrated and validated in the case study of Myrinet (a commercial, high-speed network) based network system.
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Hierarchical approach to accurate fault modeling for system evaluation
Proceedings. IEEE International Computer Performance and Dependability Symposium. IPDS'98 (Cat. No.98TB100248), 1Co-Authors: Zbigniew Kalbarczyk, G.l. Ries, J.u. Patel, M.s. Lee, Y. Xiao, Ravishankar K. IyerAbstract:This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology effects of low-level (i.e., transistor or circuit levels) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault model is obtained via simulation of the transistor-level effect of a radiation particle penetrating the device. The resulting current burst is used as a fault model in the circuit-level simulation and is injected into the nodes of a circuit/subcircuit. The latched outputs are collected in a fault dictionary and applied in conducting fault injection at the chip level under a selected workload. Faults injected at the chip level result in memory corruption, which is used as a fault model in the system-level simulation. When an Application Terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The simulation method is demonstrated and validated in the case study of Myrinet, a commercial, high-speed network. The study shows that the proposed approach offers a high confidence in the evaluation results, as the system is analyzed in presence of realistic fault conditions. It also demonstrates that the conducted analysis can be used to improve system dependability by identifying recovery mechanisms for failures observed during the experiments.
Zbigniew Kalbarczyk - One of the best experts on this subject based on the ideXlab platform.
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Hierarchical simulation approach to accurate fault modeling for system dependability evaluation
IEEE Transactions on Software Engineering, 1999Co-Authors: Zbigniew Kalbarczyk, Ravishankar K. Iyer, G.l. Ries, J.u. Patel, M.s. Lee, Y. XiaoAbstract:This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology, effects of low-level (i.e., transistor or circuit level) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault models are obtained via simulation of the transistor-level effect of a radiation particle penetrating a device. The resulting current bursts constitute the first-level fault dictionary and are used in the circuit-level simulation to determine the impact on circuit latches and flip-flops. The latched outputs constitute the next level fault dictionary in the hierarchy and are applied in conducting fault injection simulation at the chip-level under selected workloads or Application programs. Faults injected at the chip-level result in memory corruptions, which are used to form the next level fault dictionary for the system-level simulation of an Application running on simulated hardware. When an Application Terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The system in this sense can be a single workstation or a network. The simulation method is demonstrated and validated in the case study of Myrinet (a commercial, high-speed network) based network system.
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Hierarchical approach to accurate fault modeling for system evaluation
Proceedings. IEEE International Computer Performance and Dependability Symposium. IPDS'98 (Cat. No.98TB100248), 1Co-Authors: Zbigniew Kalbarczyk, G.l. Ries, J.u. Patel, M.s. Lee, Y. Xiao, Ravishankar K. IyerAbstract:This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology effects of low-level (i.e., transistor or circuit levels) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault model is obtained via simulation of the transistor-level effect of a radiation particle penetrating the device. The resulting current burst is used as a fault model in the circuit-level simulation and is injected into the nodes of a circuit/subcircuit. The latched outputs are collected in a fault dictionary and applied in conducting fault injection at the chip level under a selected workload. Faults injected at the chip level result in memory corruption, which is used as a fault model in the system-level simulation. When an Application Terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The simulation method is demonstrated and validated in the case study of Myrinet, a commercial, high-speed network. The study shows that the proposed approach offers a high confidence in the evaluation results, as the system is analyzed in presence of realistic fault conditions. It also demonstrates that the conducted analysis can be used to improve system dependability by identifying recovery mechanisms for failures observed during the experiments.
G.l. Ries - One of the best experts on this subject based on the ideXlab platform.
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Hierarchical simulation approach to accurate fault modeling for system dependability evaluation
IEEE Transactions on Software Engineering, 1999Co-Authors: Zbigniew Kalbarczyk, Ravishankar K. Iyer, G.l. Ries, J.u. Patel, M.s. Lee, Y. XiaoAbstract:This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology, effects of low-level (i.e., transistor or circuit level) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault models are obtained via simulation of the transistor-level effect of a radiation particle penetrating a device. The resulting current bursts constitute the first-level fault dictionary and are used in the circuit-level simulation to determine the impact on circuit latches and flip-flops. The latched outputs constitute the next level fault dictionary in the hierarchy and are applied in conducting fault injection simulation at the chip-level under selected workloads or Application programs. Faults injected at the chip-level result in memory corruptions, which are used to form the next level fault dictionary for the system-level simulation of an Application running on simulated hardware. When an Application Terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The system in this sense can be a single workstation or a network. The simulation method is demonstrated and validated in the case study of Myrinet (a commercial, high-speed network) based network system.
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Hierarchical approach to accurate fault modeling for system evaluation
Proceedings. IEEE International Computer Performance and Dependability Symposium. IPDS'98 (Cat. No.98TB100248), 1Co-Authors: Zbigniew Kalbarczyk, G.l. Ries, J.u. Patel, M.s. Lee, Y. Xiao, Ravishankar K. IyerAbstract:This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology effects of low-level (i.e., transistor or circuit levels) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault model is obtained via simulation of the transistor-level effect of a radiation particle penetrating the device. The resulting current burst is used as a fault model in the circuit-level simulation and is injected into the nodes of a circuit/subcircuit. The latched outputs are collected in a fault dictionary and applied in conducting fault injection at the chip level under a selected workload. Faults injected at the chip level result in memory corruption, which is used as a fault model in the system-level simulation. When an Application Terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The simulation method is demonstrated and validated in the case study of Myrinet, a commercial, high-speed network. The study shows that the proposed approach offers a high confidence in the evaluation results, as the system is analyzed in presence of realistic fault conditions. It also demonstrates that the conducted analysis can be used to improve system dependability by identifying recovery mechanisms for failures observed during the experiments.
M.s. Lee - One of the best experts on this subject based on the ideXlab platform.
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Hierarchical simulation approach to accurate fault modeling for system dependability evaluation
IEEE Transactions on Software Engineering, 1999Co-Authors: Zbigniew Kalbarczyk, Ravishankar K. Iyer, G.l. Ries, J.u. Patel, M.s. Lee, Y. XiaoAbstract:This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology, effects of low-level (i.e., transistor or circuit level) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault models are obtained via simulation of the transistor-level effect of a radiation particle penetrating a device. The resulting current bursts constitute the first-level fault dictionary and are used in the circuit-level simulation to determine the impact on circuit latches and flip-flops. The latched outputs constitute the next level fault dictionary in the hierarchy and are applied in conducting fault injection simulation at the chip-level under selected workloads or Application programs. Faults injected at the chip-level result in memory corruptions, which are used to form the next level fault dictionary for the system-level simulation of an Application running on simulated hardware. When an Application Terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The system in this sense can be a single workstation or a network. The simulation method is demonstrated and validated in the case study of Myrinet (a commercial, high-speed network) based network system.
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Hierarchical approach to accurate fault modeling for system evaluation
Proceedings. IEEE International Computer Performance and Dependability Symposium. IPDS'98 (Cat. No.98TB100248), 1Co-Authors: Zbigniew Kalbarczyk, G.l. Ries, J.u. Patel, M.s. Lee, Y. Xiao, Ravishankar K. IyerAbstract:This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology effects of low-level (i.e., transistor or circuit levels) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault model is obtained via simulation of the transistor-level effect of a radiation particle penetrating the device. The resulting current burst is used as a fault model in the circuit-level simulation and is injected into the nodes of a circuit/subcircuit. The latched outputs are collected in a fault dictionary and applied in conducting fault injection at the chip level under a selected workload. Faults injected at the chip level result in memory corruption, which is used as a fault model in the system-level simulation. When an Application Terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The simulation method is demonstrated and validated in the case study of Myrinet, a commercial, high-speed network. The study shows that the proposed approach offers a high confidence in the evaluation results, as the system is analyzed in presence of realistic fault conditions. It also demonstrates that the conducted analysis can be used to improve system dependability by identifying recovery mechanisms for failures observed during the experiments.
