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Gerrit Muller – One of the best experts on this subject based on the ideXlab platform.

  • an Architectural Framework for roadmapping towards visual strategy
    Technological Forecasting and Social Change, 2009
    Co-Authors: Robert Phaal, Gerrit Muller

    Abstract:

    Abstract Since the first application of technology roadmapping in the late 1970s to support integrated product-technology planning, roadmapping concepts and techniques have been widely adopted at product, technology, company, sector and policy levels. The roadmapping approach is flexible and scalable, and can be customized to suit many different strategic and innovation contexts. However, this demands careful planning and design, including consideration of roadmap structure, process and participation. This paper explores the issues of how to design and architect roadmaps and roadmapping processes, which is crucial if the approach is to provide a Framework for supporting effective dialogue and communication within and between organizations. The structure of the roadmap, and the process for developing and maintaining the roadmap, should be designed to serve the purpose for which the activity is intended to satisfy, providing a ‘common language and structure’ for both development and deployment of strategy.

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  • towards visual strategy an Architectural Framework for roadmapping
    Portland International Conference on Management of Engineering and Technology, 2007
    Co-Authors: Robert Phaal, Gerrit Muller

    Abstract:

    Roadmapping concepts and techniques have been widely adopted (and adapted), at product, technology, company, sector and policy levels, since its first application in the late 1970s to support integrated product-technology planning. The roadmapping approach is flexible and scalable, and can be customized to suit many different strategic and innovation contexts. However, this demands careful planning and design, including consideration of roadmap structure, process and participation. This paper explores the issues of how to design and architect roadmaps and roadmapping processes, which is crucial if the approach is to provide a Framework for supporting effective dialogue and communication within and between organizations. The structure of the roadmap, and the process for developing and maintaining the roadmap, should be designed to serve the purpose for which the activity is intended to satisfy, providing a ‘common language and structure’ for both development and deployment of strategy.

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Robert Phaal – One of the best experts on this subject based on the ideXlab platform.

  • an Architectural Framework for roadmapping towards visual strategy
    Technological Forecasting and Social Change, 2009
    Co-Authors: Robert Phaal, Gerrit Muller

    Abstract:

    Abstract Since the first application of technology roadmapping in the late 1970s to support integrated product-technology planning, roadmapping concepts and techniques have been widely adopted at product, technology, company, sector and policy levels. The roadmapping approach is flexible and scalable, and can be customized to suit many different strategic and innovation contexts. However, this demands careful planning and design, including consideration of roadmap structure, process and participation. This paper explores the issues of how to design and architect roadmaps and roadmapping processes, which is crucial if the approach is to provide a Framework for supporting effective dialogue and communication within and between organizations. The structure of the roadmap, and the process for developing and maintaining the roadmap, should be designed to serve the purpose for which the activity is intended to satisfy, providing a ‘common language and structure’ for both development and deployment of strategy.

    Free Register to Access Article

  • towards visual strategy an Architectural Framework for roadmapping
    Portland International Conference on Management of Engineering and Technology, 2007
    Co-Authors: Robert Phaal, Gerrit Muller

    Abstract:

    Roadmapping concepts and techniques have been widely adopted (and adapted), at product, technology, company, sector and policy levels, since its first application in the late 1970s to support integrated product-technology planning. The roadmapping approach is flexible and scalable, and can be customized to suit many different strategic and innovation contexts. However, this demands careful planning and design, including consideration of roadmap structure, process and participation. This paper explores the issues of how to design and architect roadmaps and roadmapping processes, which is crucial if the approach is to provide a Framework for supporting effective dialogue and communication within and between organizations. The structure of the roadmap, and the process for developing and maintaining the roadmap, should be designed to serve the purpose for which the activity is intended to satisfy, providing a ‘common language and structure’ for both development and deployment of strategy.

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Ravishankar K. Iyer – One of the best experts on this subject based on the ideXlab platform.

  • an Architectural Framework for detecting process hangs crashes
    European Dependable Computing Conference, 2005
    Co-Authors: Nithin Nakka, Zbigniew Kalbarczyk, Giacinto Paolo Saggese, Ravishankar K. Iyer

    Abstract:

    This paper addresses the challenges faced in practical implementation of heartbeat-based process/crash and hang detection. We propose an in-processor hardware module to reduce error detection latency and instrumentation overhead. Three hardware techniques integrated into the main pipeline of a superscalar processor are presented. The techniques discussed in this work are: (i) Instruction Count Heartbeat (ICH), which detects process crashes and a class of hangs where the process exists but is not executing any instructions, (ii) Infinite Loop Hang Detector (ILHD), which captures process hangs in infinite execution of legitimate loops, and (iii) Sequential Code Hang Detector (SCHD), which detects process hangs in illegal loops. The proposed design has the following unique features: 1) operating system neutral detection techniques, 2) elimination of any instrumentation for detection of all application crashes and OS hangs, and 3) an automated and light-weight compile-time instrumentation methodology to detect all process hangs (including infinite loops), the detection being performed in the hardware module at runtime. The proposed techniques can support heartbeat protocols to detect operating system/process crashes and hangs in distributed systems. Evaluation of the techniques for hang detection show a low 1.6% performance overhead and 6% memory overhead for the instrumentation. The crash detection technique does not incur any performance overhead and has a latency of a few instructions.

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  • DSN – An Architectural Framework for providing reliability and security support
    International Conference on Dependable Systems and Networks 2004, 2004
    Co-Authors: Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. Iyer

    Abstract:

    This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level Framework called the reliability and security engine (RSE), which is implemented as an integral part of a modern microprocessor. The RSE interacts with the processor through an input/output interface. The CHECK instruction, a special extension of the instruction set architecture of the processor, is the interface of the application with the RSE. The detection mechanisms described here in detail are: (I) the memory layout randomization (MLR) module, which randomizes the memory layout of a process in order to foil attackers who assume a fixed system layout, (2) the data dependency tracking (DDT) module, which tracks the dependencies among threads of a process and maintains checkpoints of shared memory pages in order to rollback the threads when an offending (potentially malicious) thread is terminated, and (3) the instruction checker module (ICM), which checks an instruction for its validity or the control-flow of the program just as the instruction enters the pipeline for execution. Performance simulations for the studied modules indicate low overhead of the proposed solutions.

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  • an Architectural Framework for providing reliability and security support
    Dependable Systems and Networks, 2004
    Co-Authors: Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. Iyer

    Abstract:

    This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level Framework called the reliability and security engine (RSE), which is implemented as an integral part of a modern microprocessor. The RSE interacts with the processor through an input/output interface. The CHECK instruction, a special extension of the instruction set architecture of the processor, is the interface of the application with the RSE. The detection mechanisms described here in detail are: (I) the memory layout randomization (MLR) module, which randomizes the memory layout of a process in order to foil attackers who assume a fixed system layout, (2) the data dependency tracking (DDT) module, which tracks the dependencies among threads of a process and maintains checkpoints of shared memory pages in order to rollback the threads when an offending (potentially malicious) thread is terminated, and (3) the instruction checker module (ICM), which checks an instruction for its validity or the control-flow of the program just as the instruction enters the pipeline for execution. Performance simulations for the studied modules indicate low overhead of the proposed solutions.

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