The Experts below are selected from a list of 68115 Experts worldwide ranked by ideXlab platform

Anna Wingkvist - One of the best experts on this subject based on the ideXlab platform.

  • using repository data for driving software architecture
    International Conference on Software Engineering, 2018
    Co-Authors: Tobias Olsson, Morgan Ericsson, Anna Wingkvist
    Abstract:

    We are in the pursuit of establishing a method for continuous data driven software architecture. We describe the problem with current methods for measuring the impact of refactoring long lived systems at the Architectural Level and architecture compliance checking. We summarize our studies of code churn, productivity and an automatic tool for compliance checking. We conclude that architecture violations seem to play an important role, but current methods are infeasible for industry practice. Finally we propose to use repository data mining to improve current methods for architecture compliance checking.

  • poster using repository data for driving software architecture
    International Conference on Software Engineering, 2018
    Co-Authors: Tobias Olsson, Morgan Ericsson, Anna Wingkvist
    Abstract:

    We are in the pursuit of establishing a method for continuous data driven software architecture.We describe the problem with current methods for measuring the impact of refactoring long lived systems at the Architectural Level and architecture compliance checking. We summarize our studies of code churn, productivity and an automatic tool for compliance checking. We conclude that architecture violations seem to play an important role, but current methods are infeasible for industry practice. Finally we propose to use repository data mining to improve current methods for architecture compliance checking.

I Bolsens - One of the best experts on this subject based on the ideXlab platform.

  • a methodology for efficient high Level dataflow simulation of mixed signal front ends of digital telecom transceivers
    Design Automation Conference, 2000
    Co-Authors: Gerd Vandersteen, Piet Wambacq, Petr Dobrovolny, S Donnay, M Engels, Yves Rolain, I Bolsens
    Abstract:

    The explosion of the telecommunications market requires miniaturization and cost-effective realization of the front-ends of transceivers for digital telecommunications. New architectures must therefore be simulated at high Level. Current methodologies and corresponding tools suffer from common drawbacks, such as lower accuracy, slow simulation speed, etc. A new methodology has been developped for the efficient simulation, at the Architectural Level, of mixed-signal front-ends of digital telecom transceivers. The efficient execution is obtained using a multi-rate, multi-carrier signal representation together with a dataflow simulation scheme which switches dynamically towards the most efficient signal processing technique available. An implementation of this methodology shows both excellent runtimes and a high accuracy.

  • compact modeling of nonlinear distortion in analog communication circuits
    Design Automation and Test in Europe, 2000
    Co-Authors: Piet Wambacq, Petr Dobrovolny, S Donnay, M Engels, I Bolsens
    Abstract:

    The design of analog front-ends of digital telecommunication transceivers requires simulations at the Architectural Level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the Architectural Level, especially when the nonlinear behavior is frequency dependent. This paper describes a method to derive a bottom-up model of nonlinear analog continuous-time circuits used in communication systems. The models take into account frequency dependence of the nonlinear behavior, making them suitable for wideband applications. Such model consists of a block diagram that corresponds to the most important contributions to the second- and third-order Volterra kernels of the output quantity (voltage or current) of a circuit. The examples in this paper, a high-Level model of a CMOS low-noise amplifier and an active lowpass filter, demonstrate that the generated models can be efficiently evaluated in high-Level dataflow-type simulations of mixed-signal front-ends and that they yield insight in the nonlinear behavior of the analog front-end blocks.

  • Compact Modeling of Nonlinear Disto Rtion in Analog Communication Circuits
    2000
    Co-Authors: Piet Wambacq, S Donnay, M Engels, Petr Dobrovoln, I Bolsens
    Abstract:

    The design of analog front-ends of digital telecommunication transceivers requires simulations at the Architectural Level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the Architectural Level, especially when the nonlinear behavior is frequency dependent. This paper describes a method to derive a bottom -up model of nonlinear analog continuous-time circuits used in communication systems. The models take into account frequency dependence of the nonlinear behavior, making them suitable for wideband applications. Such model consists of a block diagram that corresponds to the most important contributions to the second- and thirdorder Volterra kernels of the output quantity (voltage or current) of a circuit. The examples in this paper, a highLevel model of a CMOS low-noise amplifier and an active lowpass filter, demonstrate that the generated models can be efficiently evaluated in high-Level dataflow-type simulations of mixed-signal front-ends and that they yield insight in the nonlinear behavior of the analog front-end blocks

Sharad Malik - One of the best experts on this subject based on the ideXlab platform.

  • a power model for routers modeling alpha 21364 and infiniband routers
    IEEE Micro, 2003
    Co-Authors: Hangsheng Wang, Lishiuan Peh, Sharad Malik
    Abstract:

    As interconnection networks proliferate to many new applications, a low-latency high-throughput fabric no longer suffices. An Architectural-Level power model for interconnection network routers will let researchers and designers easily factor in power when exploring Architectural tradeoffs.

  • orion a power performance simulator for interconnection networks
    International Symposium on Microarchitecture, 2002
    Co-Authors: Hangsheng Wang, Xinping Zhu, Lishiuan Peh, Sharad Malik
    Abstract:

    With the prevalence of server blades and systems-on-a-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limited tool support available for their design. While performance simulators have been built that enable performance estimation while varying network parameters, these cover only one metric of interest in modern designs. System power consumption is increasingly becoming equally, if not more important than performance. It is now critical to get detailed power-performance tradeoff information early in the microArchitectural design cycle. This is especially so as interconnection networks consume a significant fraction of total system power. It is exactly this gap that the work presented in this paper aims to fill.We present Orion, a power-performance interconnection network simulator that is capable of providing detailed power characteristics, in addition to performance characteristics, to enable rapid power-performance trade-offs at the Architectural-Level. This capability is provided within a general framework that builds a simulator starting from a microArchitectural specification of the interconnection network. A key component of this construction is the Architectural-Level parameterized power models that we have derived as part of this effort. Using component power models and a synthesized efficient power (and performance) simulator, a microarchitect can rapidly explore the design space. As case studies, we demonstrate the use of Orion in determining optimal system parameters, in examining the effect of diverse traffic conditions, as well as evaluating new network microarchitectures. In each of the above, the ability to simultaneously monitor power and performance is key in determining suitable microarchitectures.

  • a power model for routers modeling alpha 21364 and infiniband routers
    High Performance Interconnects, 2002
    Co-Authors: Hangsheng Wang, Lishiuan Peh, Sharad Malik
    Abstract:

    As interconnection networks proliferate to many new applications, a low-latency high-throughput fabric is no longer sufficient. Applications are becoming power-constrained. We propose an Architectural-Level power model for interconnection network routers that will allow researchers and designers to easily factor in power when exploring Architectural trade-offs. We applied our model to two commercial routers - the integrated Alpha 21364 router and the IBM 8-port 12X InfiniBand router and show that the different micro-architectures lead to vastly different power consumption and distribution estimates.

Tobias Olsson - One of the best experts on this subject based on the ideXlab platform.

  • using repository data for driving software architecture
    International Conference on Software Engineering, 2018
    Co-Authors: Tobias Olsson, Morgan Ericsson, Anna Wingkvist
    Abstract:

    We are in the pursuit of establishing a method for continuous data driven software architecture. We describe the problem with current methods for measuring the impact of refactoring long lived systems at the Architectural Level and architecture compliance checking. We summarize our studies of code churn, productivity and an automatic tool for compliance checking. We conclude that architecture violations seem to play an important role, but current methods are infeasible for industry practice. Finally we propose to use repository data mining to improve current methods for architecture compliance checking.

  • poster using repository data for driving software architecture
    International Conference on Software Engineering, 2018
    Co-Authors: Tobias Olsson, Morgan Ericsson, Anna Wingkvist
    Abstract:

    We are in the pursuit of establishing a method for continuous data driven software architecture.We describe the problem with current methods for measuring the impact of refactoring long lived systems at the Architectural Level and architecture compliance checking. We summarize our studies of code churn, productivity and an automatic tool for compliance checking. We conclude that architecture violations seem to play an important role, but current methods are infeasible for industry practice. Finally we propose to use repository data mining to improve current methods for architecture compliance checking.

Jan M Rabaey - One of the best experts on this subject based on the ideXlab platform.

  • power estimation for high Level synthesis
    European Design Automation Conference, 1993
    Co-Authors: Paul E Landman, Jan M Rabaey
    Abstract:

    Techniques for rapidly and accurately estimating power consumption based on high Level descriptions of system architectures are described. This approach, based on stochastic modeling of bus statistics, achieves the accuracy traditionally associated with gate and circuit Level estimation tools while exploiting the reduced computational complexity offered by the Architectural Level of abstraction. The results presented indicate an estimation accuracy within 9.4% of gate Level simulations, while existing high Level techniques can be off 80% or more. >