The Experts below are selected from a list of 53019 Experts worldwide ranked by ideXlab platform
Jaehyuk Huh - One of the best experts on this subject based on the ideXlab platform.
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vcache Architectural Support for transparent and isolated virtual llcs in virtualized environments
International Symposium on Microarchitecture, 2015Co-Authors: Daehoon Kim, Hwanju Kim, Nam Sung Kim, Jaehyuk HuhAbstract:A key role of virtualization is to give an illusion that a consolidated workload runs on a dedicated machine although the underlying resources are actively shared by multiple workloads. Technical advances have enabled a virtual machine (VM) to exercise many shared resources of a machine in a transparent and isolated manner. However, such an illusion of resource dedication has not been Supported for the last-level cache (LLC), although the LLC is the largest on-chip shared resource with a significant performance impact. In this paper, we propose vCache--Architectural Support to provide a transparent and isolated virtual LLC (vLLC) for each VM and interfaces to manage the vLLC. More specifically, this study first proposes Architectural Support for the guest OS of a VM to index the LLC with its guest physical address instead of a host physical address. This in turn allows that the guest OS transparently view its vLLC and preserve the effectiveness of its page placement policy. Second, this study extends the Architectural Support for each VM to keep its vLLC strongly isolated from other VMs. Such resource dedication is critical to offer performance isolation and preserve vLLC transparency for each VM in a highly consolidated machine. With little hardware overhead, vCache can facilitate various unchartered vLLC capacity-based services for the public clouds while providing up to 17% higher performance than a traditional virtualized system.
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MICRO - vCache: Architectural Support for transparent and isolated virtual LLCs in virtualized environments
Proceedings of the 48th International Symposium on Microarchitecture, 2015Co-Authors: Daehoon Kim, Hwanju Kim, Nam Sung Kim, Jaehyuk HuhAbstract:A key role of virtualization is to give an illusion that a consolidated workload runs on a dedicated machine although the underlying resources are actively shared by multiple workloads. Technical advances have enabled a virtual machine (VM) to exercise many shared resources of a machine in a transparent and isolated manner. However, such an illusion of resource dedication has not been Supported for the last-level cache (LLC), although the LLC is the largest on-chip shared resource with a significant performance impact. In this paper, we propose vCache--Architectural Support to provide a transparent and isolated virtual LLC (vLLC) for each VM and interfaces to manage the vLLC. More specifically, this study first proposes Architectural Support for the guest OS of a VM to index the LLC with its guest physical address instead of a host physical address. This in turn allows that the guest OS transparently view its vLLC and preserve the effectiveness of its page placement policy. Second, this study extends the Architectural Support for each VM to keep its vLLC strongly isolated from other VMs. Such resource dedication is critical to offer performance isolation and preserve vLLC transparency for each VM in a highly consolidated machine. With little hardware overhead, vCache can facilitate various unchartered vLLC capacity-based services for the public clouds while providing up to 17% higher performance than a traditional virtualized system.
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Architectural Support for secure virtualization under a vulnerable hypervisor
International Symposium on Microarchitecture, 2011Co-Authors: Seongwook Jin, Jeongseob Ahn, Sanghoon Cha, Jaehyuk HuhAbstract:Although cloud computing has emerged as a promising future computing model, security concerns due to malicious tenants have been deterring its fast adoption. In cloud computing, multiple tenants may share physical systems by using virtualization techniques. In such a virtualized system, a software hypervisor creates virtual machines (VMs) from the physical system, and provides each user with an isolated VM. However, the hypervisor, with a full control over hardware resources, can access the memory pages of guest VMs without any restriction. By compromising the hypervisor, a malicious user can access the memory contents of the VMs used by other users. In this paper, we propose a hardware-based mechanism to protect the memory of guest VMs from unauthorized accesses, even with an untrusted hypervisor. With this mechanism, memory isolation is provided by the secure hardware, which is much less vulnerable than the software hypervisor. The proposed mechanism extends the current hardware Support for memory virtualization with a small extra hardware cost. The hypervisor can still flexibly allocate physical memory pages to virtual machines for efficient resource management. However, the hypervisor can update nested page tables only through the secure hardware mechanism, which verifies each mapping change. Using the hardware-oriented mechanism in each system securing guest VMs under a vulnerable hypervisor, this paper also proposes a cloud system architecture, which Supports the authenticated launch and migration of guest VMs.
Josep Torrellas - One of the best experts on this subject based on the ideXlab platform.
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shortcut Architectural Support for fast object access in scripting languages
International Symposium on Computer Architecture, 2017Co-Authors: Jiho Choi, María Jesús Garzarán, Thomas Shull, Josep TorrellasAbstract:The same flexibility that makes dynamic scripting languages appealing to programmers is also the primary cause of their low performance. To access objects of potentially different types, the compiler creates a dispatcher with a series of if statements, each performing a comparison to a type and a jump to a handler. This induces major overhead in instructions executed and branches mispredicted. This paper proposes Architectural Support to significantly improve the efficiency of accesses to objects. The idea is to modify the instruction that calls the dispatcher so that, under most conditions, it skips most of the branches and instructions needed to reach the correct handler, and sometimes even the execution of the handler itself. Our novel architecture, called ShortCut, performs two levels of optimization. Its Plain design transforms the call to the dispatcher into a call to the correct handler --- bypassing the whole dispatcher execution. Its Aggressive design transforms the call to the dispatcher into a simple load or store --- bypassing the execution of both dispatcher and handler. We implement the ShortCut software in the state-of-the-art Google V8 JIT compiler, and the ShortCut hardware in a simulator. We evaluate ShortCut with the Octane and SunSpider JavaScript application suites. Plain ShortCut reduces the average execution time of the applications by 30% running under the baseline compiler, and by 11% running under the maximum level of compiler optimization. Aggressive ShortCut performs only slightly better.
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colorama Architectural Support for data centric synchronization
High-Performance Computer Architecture, 2007Co-Authors: Luis Ceze, Pablo Montesinos, C Von Praun, Josep TorrellasAbstract:With the advent of ubiquitous multi-core architectures, a major challenge is to simplify parallel programming. One way to tame one of the main sources of programming complexity, namely synchronization, is transactional memory (TM). However, we argue that TM does not go far enough, since the programmer still needs nonlocal reasoning to decide where to place transactions in the code. A significant improvement to the art is data-centric synchronization (DCS), where the programmer uses local reasoning to assign synchronization constraints to data. Based on these, the system automatically infers critical sections and inserts synchronization operations. This paper proposes novel Architectural Support to make DCS feasible, and describes its programming model and interface. The proposal, called Colorama, needs only modest hardware extensions, Supports general-purpose, pointer-based languages such as C/C++ and, in our opinion, can substantially simplify the task of writing new parallel programs
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HPCA - Colorama: Architectural Support for Data-Centric Synchronization
2007 IEEE 13th International Symposium on High Performance Computer Architecture, 2007Co-Authors: Luis Ceze, Pablo Montesinos, C Von Praun, Josep TorrellasAbstract:With the advent of ubiquitous multi-core architectures, a major challenge is to simplify parallel programming. One way to tame one of the main sources of programming complexity, namely synchronization, is transactional memory (TM). However, we argue that TM does not go far enough, since the programmer still needs nonlocal reasoning to decide where to place transactions in the code. A significant improvement to the art is data-centric synchronization (DCS), where the programmer uses local reasoning to assign synchronization constraints to data. Based on these, the system automatically infers critical sections and inserts synchronization operations. This paper proposes novel Architectural Support to make DCS feasible, and describes its programming model and interface. The proposal, called Colorama, needs only modest hardware extensions, Supports general-purpose, pointer-based languages such as C/C++ and, in our opinion, can substantially simplify the task of writing new parallel programs
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efficient and flexible Architectural Support for dynamic monitoring
ACM Transactions on Architecture and Code Optimization, 2005Co-Authors: Yuanyuan Zhou, Feng Qin, Pin Zhou, Wei Liu, Josep TorrellasAbstract:Recent impressive performance improvements in computer architecture have not led to significant gains in the case of debugging. Software debugging often relies on inserting run-time software checks. In many cases, however, it is hard to find the root cause of a bug. Moreover, program execution typically slows down significantly, often by 10--100 times.To address this problem, this paper introduces the intelligent watcher (iWatcher), a novel Architectural scheme to monitor dynamic execution automatically, flexibly, and with minimal overhead. iWatcher associates program-specified monitoring functions with memory locations. When any such location is accessed, the monitoring function is automatically triggered with low overhead. To further reduce overhead and Support rollback, iWatcher can optionally leverage thread-level speculation (TLS). The iWatcher architecture can be used to detect various bugs, including buffer overflow, accessing freed locations, memory leaks, stack-smashing and value-invariant violations. To evaluate iWatcher, we use seven applications with various real and injected bugs. Our results show that iWatcher detects many more software bugs than Valgrind, a well-known open-source bug detector. Moreover, iWatcher only induces a 0.1--179p execution overhead, which is orders of magnitude less than Valgrind. Our sensitivity study shows that even with 20p of the dynamic loads monitored in a program, iWatcher adds only 72--182p overhead. Finally, TLS is effective at reducing overheads for programs with substantial monitoring.
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iwatcher efficient Architectural Support for software debugging
International Symposium on Computer Architecture, 2004Co-Authors: Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep TorrellasAbstract:Recent impressive performance improvements in computer architecturehave not led to significant gains in ease of debugging.Software debugging often relies on inserting run-time softwarechecks. In many cases, however, it is hard to find the root causeof a bug. Moreover, program execution typically slows down significantly,often by 10-100 times.To address this problem, this paper introduces the IntelligentWatcher (iWatcher), novel Architectural Support to monitor dynamicexecution with minimal overhead, automatically, and flexibly.iWatcher associates program-specified monitoring functionswith memory locations. When any such location is accessed, themonitoring function is automatically triggered with low overhead.To further reduce overhead and Support rollback, iWatcher canleverage Thread-Level Speculation (TLS). To test iWatcher, we useapplications with various bugs. Our results show that iWatcher detectsmany more software bugs than Valgrind, a well-known open-sourcebug detector. Moreover, iWatcher only induces a 4-80%execution overhead, which is orders of magnitude less than Valgrind.Even with 20% of the dynamic loads monitored in a program,iWatcher adds only 66-174% overhead. Finally, TLS is effective atreducing overheads for programs with substantial monitoring.
Dan Alistarh - One of the best experts on this subject based on the ideXlab platform.
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lease release Architectural Support for scaling contended data structures
Parallel Computing, 2017Co-Authors: Syed Kamran Haider, William C Hasenplaugh, Dan AlistarhAbstract:High memory contention is generally agreed to be a worst-case scenario for concurrent data structures. There has been a significant amount of research effort spent investigating designs that minimize contention, and several programming techniques have been proposed to mitigate its effects. However, there are currently few Architectural mechanisms to allow scaling contended data structures at high thread counts. In this article, we investigate hardware Support for scalable contended data structures. We propose Lease/Release, a simple addition to standard directory-based MESI cache coherence protocols, allowing participants to lease memory, at the granularity of cache lines, by delaying coherence messages for a short, bounded period of time. Our analysis shows that Lease/Release can significantly reduce the overheads of contention for both non-blocking (lock-free) and lock-based data structure implementations while ensuring that no deadlocks are introduced. We validate Lease/Release empirically on the Graphite multiprocessor simulator on a range of data structures, including queue, stack, and priority queue implementations, as well as on transactional applications. Results show that Lease/Release consistently improves both throughput and energy usage, by up to 5x, both for lock-free and lock-based data structure designs.
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lease release Architectural Support for scaling contended data structures
ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016Co-Authors: Syed Kamran Haider, William C Hasenplaugh, Dan AlistarhAbstract:High memory contention is generally agreed to be a worst-case scenario for concurrent data structures. There has been a significant amount of research effort spent investigating designs which minimize contention, and several programming techniques have been proposed to mitigate its effects. However, there are currently few Architectural mechanisms to allow scaling contended data structures at high thread counts. In this paper, we investigate hardware Support for scalable contended data structures. We propose Lease/Release, a simple addition to standard directory-based MSI cache coherence protocols, allowing participants to lease memory, at the granularity of cache lines, by delaying coherence messages for a short, bounded period of time. Our analysis shows that Lease/Release can significantly reduce the overheads of contention for both non-blocking (lock-free) and lock-based data structure implementations, while ensuring that no deadlocks are introduced. We validate Lease/Release empirically on the Graphite multiprocessor simulator, on a range of data structures, including queue, stack, and priority queue implementations, as well as on transactional applications. Results show that Lease/Release consistently improves both throughput and energy usage, by up to 5x, both for lock-free and lock-based data structure designs.
Quinn A Jacobson - One of the best experts on this subject based on the ideXlab platform.
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Architectural Support for software transactional memory
International Symposium on Microarchitecture, 2006Co-Authors: Bratin Saha, Alireza Adltabatabai, Quinn A JacobsonAbstract:Transactional memory provides a concurrency control mechanism that avoids many of the pitfalls of lock-based synchronization. Researchers have proposed several different implementations of transactional memory, broadly classified into software transactional memory (STM) and hardware transactional memory (HTM). Both approaches have their pros and cons: STMs provide rich and flexible transactional semantics on stock processors but incur significant overheads. HTMs, on the other hand, provide high performance but implement restricted semantics or add significant hardware complexity. This paper is the first to propose Architectural Support for accelerating transactions executed entirely in software. We propose instruction set architecture (ISA) extensions and novel hardware mechanisms that improve STM performance. We adapt a high-performance STM algorithm Supporting rich transactional semantics to our ISA extensions (called hardware accelerated software transactional memory or HASTM). HASTM accelerates fully virtualized nested transactions, Supports language integration, and provides both object-based and cache-line based conflict detection. We have implemented HASTM in an accurate multi-core IA32 simulator. Our simulation results show that (1) HASTM single-thread performance is comparable to a conventional HTM implementation; (2) HASTM scaling is comparable to a STM implementation; and (3) HASTM is resilient to spurious aborts and can scale better than HTM in a multi-core setting. Thus, HASTM provides the flexibility and rich semantics of STM, while giving the performance of HTM.
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MICRO - Architectural Support for Software Transactional Memory
2006 39th Annual IEEE ACM International Symposium on Microarchitecture (MICRO'06), 2006Co-Authors: Bratin Saha, Ali-reza Adl-tabatabai, Quinn A JacobsonAbstract:Transactional memory provides a concurrency control mechanism that avoids many of the pitfalls of lock-based synchronization. Researchers have proposed several different implementations of transactional memory, broadly classified into software transactional memory (STM) and hardware transactional memory (HTM). Both approaches have their pros and cons: STMs provide rich and flexible transactional semantics on stock processors but incur significant overheads. HTMs, on the other hand, provide high performance but implement restricted semantics or add significant hardware complexity. This paper is the first to propose Architectural Support for accelerating transactions executed entirely in software. We propose instruction set architecture (ISA) extensions and novel hardware mechanisms that improve STM performance. We adapt a high-performance STM algorithm Supporting rich transactional semantics to our ISA extensions (called hardware accelerated software transactional memory or HASTM). HASTM accelerates fully virtualized nested transactions, Supports language integration, and provides both object-based and cache-line based conflict detection. We have implemented HASTM in an accurate multi-core IA32 simulator. Our simulation results show that (1) HASTM single-thread performance is comparable to a conventional HTM implementation; (2) HASTM scaling is comparable to a STM implementation; and (3) HASTM is resilient to spurious aborts and can scale better than HTM in a multi-core setting. Thus, HASTM provides the flexibility and rich semantics of STM, while giving the performance of HTM.
Syed Kamran Haider - One of the best experts on this subject based on the ideXlab platform.
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lease release Architectural Support for scaling contended data structures
Parallel Computing, 2017Co-Authors: Syed Kamran Haider, William C Hasenplaugh, Dan AlistarhAbstract:High memory contention is generally agreed to be a worst-case scenario for concurrent data structures. There has been a significant amount of research effort spent investigating designs that minimize contention, and several programming techniques have been proposed to mitigate its effects. However, there are currently few Architectural mechanisms to allow scaling contended data structures at high thread counts. In this article, we investigate hardware Support for scalable contended data structures. We propose Lease/Release, a simple addition to standard directory-based MESI cache coherence protocols, allowing participants to lease memory, at the granularity of cache lines, by delaying coherence messages for a short, bounded period of time. Our analysis shows that Lease/Release can significantly reduce the overheads of contention for both non-blocking (lock-free) and lock-based data structure implementations while ensuring that no deadlocks are introduced. We validate Lease/Release empirically on the Graphite multiprocessor simulator on a range of data structures, including queue, stack, and priority queue implementations, as well as on transactional applications. Results show that Lease/Release consistently improves both throughput and energy usage, by up to 5x, both for lock-free and lock-based data structure designs.
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lease release Architectural Support for scaling contended data structures
ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016Co-Authors: Syed Kamran Haider, William C Hasenplaugh, Dan AlistarhAbstract:High memory contention is generally agreed to be a worst-case scenario for concurrent data structures. There has been a significant amount of research effort spent investigating designs which minimize contention, and several programming techniques have been proposed to mitigate its effects. However, there are currently few Architectural mechanisms to allow scaling contended data structures at high thread counts. In this paper, we investigate hardware Support for scalable contended data structures. We propose Lease/Release, a simple addition to standard directory-based MSI cache coherence protocols, allowing participants to lease memory, at the granularity of cache lines, by delaying coherence messages for a short, bounded period of time. Our analysis shows that Lease/Release can significantly reduce the overheads of contention for both non-blocking (lock-free) and lock-based data structure implementations, while ensuring that no deadlocks are introduced. We validate Lease/Release empirically on the Graphite multiprocessor simulator, on a range of data structures, including queue, stack, and priority queue implementations, as well as on transactional applications. Results show that Lease/Release consistently improves both throughput and energy usage, by up to 5x, both for lock-free and lock-based data structure designs.