The Experts below are selected from a list of 270912 Experts worldwide ranked by ideXlab platform
Jude A. Rivers - One of the best experts on this subject based on the ideXlab platform.
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DSN - A Framework for Architecture-Level Lifetime Reliability Modeling
37th Annual IEEE IFIP International Conference on Dependable Systems and Networks (DSN'07), 2007Co-Authors: Jeonghee Shin, Jude A. Rivers, Victor Zyuban, Pradip BoseAbstract:This paper tackles the issue of modeling chip lifetime reliability at the Architecture Level. We propose a new and robust structure-aware lifetime reliability model at the Architecture-Level, where devices only vulnerable to failure mechanisms and the effective stress condition of these devices are taken into account for the failure rate of microArchitecture structures. In addition, we present this reliability analysis framework based on a new concept, called the FIT of reference circuit or FORC, which allows architects to quantify failure rates without having to delve into low-Level circuit- and technology-specific details of the implemented Architecture. This is done through a onetime characterization of a reference circuit needed to quantify the reference FITs for each class of modeled failure mechanisms for a given technology and implementation style. With this new reliability modeling framework, architects are empowered to proceed with Architecture-Level reliability analysis independent of technological and environmental parameters.
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DSN - Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions
37th Annual IEEE IFIP International Conference on Dependable Systems and Networks (DSN'07), 2007Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:This paper concerns the validity of a widely used method for estimating the Architecture-Level mean time to failure (MTTF) due to soft errors. The method first calculates the failure rate for an Architecture-Level component as the product of its raw error rate and an Architecture vulnerability factor (AVF). Next, the method calculates the system failure rate as the sum of the failure rates (SOFR) of all components, and the system MTTF as the reciprocal of this failure rate. Both steps make significant assumptions. We investigate the validity of the AVF+SOFR method across a large design space, using both mathematical and experimental techniques with real program traces from SPEC 2000 benchmarks and synthesized traces to simulate longer real-world workloads. We show that AVF+SOFR is valid for most of the realistic cases under current raw error rates. However, for some realistic combinations of large systems, long-running workloads with large phases, and/or large raw error rates, the MTTF calculated using AVF+SOFR shows significant-discrepancies from that using first principles. We also show that SoftArch, a previously proposed alternative method that does not make the AVF+SOFR assumptions, does not exhibit the above discrepancies.
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softarch an Architecture Level tool for modeling and analyzing soft errors
Dependable Systems and Networks, 2005Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:Soft errors are a growing concern for processor reliability. Recent work has motivated Architecture-Level studies of soft errors since the Architecture can mask many raw errors and architectural solutions can exploit workload knowledge. This paper proposes a model and tool, called SoftArch, to enable analysis of soft errors at the Architecture-Level in modern processors. SoftArch is based on a probabilistic model of the error generation and propagation process in a processor. Compared to prior Architecture-Level tools, SoftArch is more comprehensive or faster. We demonstrate the use of SoftArch for an out-of-order superscalar processor running SPEC2000 benchmarks. Our results are consistent with, but more comprehensive than, prior work, and motivate selective and dynamic Architecture-Level soft error protection mechanisms.
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Scaling of Architecture Level Soft Error Rate for Superscalar Processors
2005Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:Soft errors are a growing concern for processor reliability. Recent studies have motivated Architecture Level studies of soft errors. It has been shown that the Architecture Level has a large derating effect on the raw processor error rate. In this paper, we quantify the impact of technology scaling on the processor soft error rate, taking the Architecture Level derating effects and workload characteristics into consideration. For our evaluation, we use SoftArch to quantify the derating factor and soft error rate (SER) for different structures in a modern superscalar processor running SPEC2000 benchmarks. We compare the SERs across four different technologies ranging from 180nm to 65nm with the same microArchitecture. We find that with scaling, the derating factors for logic structures often decrease, the derating factors for storage elements remain roughly unchanged, and the FIT rate for the full processor roughly follows the trend for the raw SER of storage structures (i.e., the FIT rate.increases from 180nm to 90nm and decreases from 90nm to 65nm.
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DSN - SoftArch: an Architecture-Level tool for modeling and analyzing soft errors
2005 International Conference on Dependable Systems and Networks (DSN'05), 2005Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:Soft errors are a growing concern for processor reliability. Recent work has motivated Architecture-Level studies of soft errors since the Architecture can mask many raw errors and architectural solutions can exploit workload knowledge. This paper proposes a model and tool, called SoftArch, to enable analysis of soft errors at the Architecture-Level in modern processors. SoftArch is based on a probabilistic model of the error generation and propagation process in a processor. Compared to prior Architecture-Level tools, SoftArch is more comprehensive or faster. We demonstrate the use of SoftArch for an out-of-order superscalar processor running SPEC2000 benchmarks. Our results are consistent with, but more comprehensive than, prior work, and motivate selective and dynamic Architecture-Level soft error protection mechanisms.
Jan Bosch - One of the best experts on this subject based on the ideXlab platform.
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Architecture-Level modifiability analysis (ALMA)
Journal of Systems and Software, 2004Co-Authors: Perolof Bengtsson, N.h. Lassing, Jan Bosch, Hans Van VlietAbstract:Several studies have shown that 50-70% of the total lifecycle cost for a software system is spent on evolving the system. Organizations aim to reduce the cost of these adaptations, by addressing modifiability during the system's development. The software Architecture plays an important role in achieving this, but few methods for Architecture-Level modifiability analysis exist. Independently, the authors have been working on scenario-based software Architecture analysis methods that focus exclusively on modifiability. Combining these methods led to Architecture-Level modifiability analysis (ALMA), a unified Architecture-Level analysis method that focuses on modifiability, distinguishes multiple analysis goals, has explicit assumptions and provides repeatable techniques for performing the steps. ALMA consists of five main steps, i.e. goal selection, software Architecture description, change scenario elicitation, change scenario evaluation and interpretation. The method has been validated through its application in several cases, including software Architectures at Ericsson Software Technology, DFDS Fraktarna, Althin Medical, the Dutch Department of Defense and the Dutch Tax and Customs Administration. © 2003 Elsevier Inc. All rights reserved
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Architecture-Level modifiability analysis (ALMA)
Journal of Systems and Software, 2003Co-Authors: Perolof Bengtsson, N.h. Lassing, Jan Bosch, Hans Van VlietAbstract:Several studies have shown that 50-70% of the total lifecycle cost for a software system is spent on evolving the system. Organizations aim to reduce the cost of these adaptations, by addressing modifiability during the system's development. The software Architecture plays an important role in achieving this, but few methods for Architecture-Level modifiability analysis exist. Independently, the authors have been working on scenario-based software Architecture analysis methods that focus exclusively on modifiability. Combining these methods led to Architecture-Level modifiability analysis (ALMA), a unified Architecture-Level analysis method that focuses on modifiability, distinguishes multiple analysis goals, has explicit assumptions and provides repeatable techniques for performing the steps. ALMA consists of five main steps, i.e. goal selection, software Architecture description, change scenario elicitation, change scenario evaluation and interpretation. The method has been validated through its application in several cases, including software Architectures at Ericsson Software Technology, DFDS Fraktarna, Althin Medical, the Dutch Department of Defense and the Dutch Tax and Customs Administration.
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Experiences with ALMA: Architecture-Level modifiability analysis
Journal of Systems and Software, 2002Co-Authors: N.h. Lassing, Hans Van Vliet, Perlof Bengtsson, Jan BoschAbstract:Modifiability is an important quality for software systems, because a large part of the costs associated with these systems is spent on modifications. The effort, and therefore cost, that is required for these modifications is largely determined by a system's software Architecture. Analysis of software Architectures is therefore an important technique to achieve modifiability and reduce maintenance costs. However, few techniques for software Architecture analysis currently exist. Based on our experiences with software Architecture analysis of modifiability, we have developed ALMA, an Architecture-Level modifiability analysis method consisting of five steps. In this paper we report on our experiences with ALMA. We illustrate our experiences with examples from two case studies of software Architecture analysis of modifiability. These case studies concern a system for mobile positioning at Ericsson Software Technology AB and a system for freight handling at DFDS Fraktarna. Our experiences are related to each step of the analysis process. In addition, we made some observations on software Architecture analysis of modifiability in general.
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Architecture Level prediction of software maintenance
Conference on Software Maintenance and Reengineering, 1999Co-Authors: Perolof Bengtsson, Jan BoschAbstract:A method for the prediction of software maintainability during software Architecture design is presented. The method takes: the requirement specification; the design of the Architecture; expertise from software engineers; and, possibly, historical data as input and generates a prediction of the average effort for a maintenance task. Scenarios are used by the method to concretize the maintainability requirements and to analyze the Architecture for the prediction of the maintainability. The method is formulated based on extensive experience in software Architecture design and detailed design and exemplified using the design of software Architecture for a haemo dialysis machine. Experiments for evaluation and validation of the method are ongoing and future work.
Samuel Kounev - One of the best experts on this subject based on the ideXlab platform.
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Architecture Level software performance abstractions for online performance prediction
Science of Computer Programming, 2014Co-Authors: Fabian Brosig, Nikolaus Huber, Samuel KounevAbstract:Abstract Modern service-oriented enterprise systems have increasingly complex and dynamic loosely-coupled Architectures that often exhibit poor performance and resource efficiency and have high operating costs. This is due to the inability to predict at run-time the effect of workload changes on performance-relevant application-Level dependencies and adapt the system configuration accordingly. Architecture-Level performance models provide a powerful tool for performance prediction, however, current approaches to modeling the context of software components are not suitable for use at run-time. In this paper, we analyze typical online performance prediction scenarios and propose a performance meta-model for (i) expressing and resolving parameter and context dependencies, (ii) modeling service abstractions at different Levels of granularity and (iii) modeling the deployment of software components in complex resource landscapes. The presented meta-model is a subset of the Descartes Meta-Model (DMM) for online performance prediction, specifically designed for use in online scenarios. We motivate and validate our approach in the context of realistic and representative online performance prediction scenarios based on the SPECjEnterprise2010 standard benchmark.
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ICPE - Performance queries for Architecture-Level performance models
Proceedings of the 5th ACM SPEC international conference on Performance engineering, 2014Co-Authors: Fabian Gorsler, Fabian Brosig, Samuel KounevAbstract:Over the past few decades, many performance modeling formalisms and prediction techniques for software Architectures have been developed in the performance engineering community. However, using a performance model to predict the performance of a software system normally requires extensive experience with the respective modeling formalism and involves a number of complex and time consuming manual steps. In this paper, we propose a generic declarative interface to performance prediction techniques to simplify and automate the process of using Architecture-Level software performance models for performance analysis. The proposed Descartes Query Language (DQL) is a language to express the demanded performance metrics for prediction as well as the goals and constraints of the specific prediction scenario. It reduces the manual effort and learning curve in working with performance models by a unified interface independent of the employed modeling formalism. We evaluate the applicability and benefits of the proposed approach in the context of several representative case studies.
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Modeling run-time adaptation at the system Architecture Level in dynamic service-oriented environments
Service Oriented Computing and Applications, 2014Co-Authors: Nikolaus Huber, Fabian Brosig, André Hoorn, Anne Koziolek, Samuel KounevAbstract:Today, software systems are more and more executed in dynamic, virtualized environments. These environments host diverse applications of different parties, sharing the underlying resources. The goal of this resource sharing is to utilize resources efficiently while ensuring that quality-of-service requirements are continuously satisfied. In such scenarios, complex adaptations to changes in the system environment are still largely performed manually by humans. Over the past decade, autonomic self-adaptation techniques aiming to minimize human intervention have become increasingly popular. However, given that adaptation processes are usually highly system-specific, it is a challenge to abstract from system details, enabling the reuse of adaptation strategies. In this paper, we present S/T/A, a modeling language to describe system adaptation processes at the system Architecture Level in a generic, human-understandable and reusable way. We apply our approach to multiple different realistic contexts (dynamic resource allocation, run-time adaptation planning, etc.). The results show how a holistic model-based approach can close the gap between complex manual adaptations and their autonomous execution.
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ICPE - A generic approach for Architecture-Level performance modeling and prediction of virtualized storage systems
Proceedings of the ACM SPEC international conference on International conference on performance engineering - ICPE '13, 2013Co-Authors: Qais Noorshams, Samuel Kounev, Andreas Rentschler, Ralf ReussnerAbstract:Virtualized environments introduce an additional abstraction layer on top of physical resources to enable the collective resource usage by multiple systems. With the rise of I/O-intensive applications, however, the virtualized storage of such shared environments can quickly become a bottleneck and lead to performance and scalability issues. The latter can be avoided through careful design of the application Architecture and systematic capacity planning throughout the system life cycle. In current practice, however, virtualized storage and its performance-influencing design decisions are often neglected or treated as a black-box. In this work-in-progress paper, we propose a generic approach for performance modeling and prediction of virtualized storage systems at the software Architecture Level. More specifically, we propose two performance modeling approaches of virtualized systems. Furthermore, we propose two approaches how the performance models can be combined with Architecture-Level performance models. The goal is to cope with the increasing complexity of virtualized storage systems with the benefit of intuitive software Architecture-Level models.
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Automated extraction of Architecture-Level performance models of distributed component-based systems
2011 26th IEEE/ACM International Conference on Automated Software Engineering (ASE 2011), 2011Co-Authors: Fabian Brosig, Nikolaus Huber, Samuel KounevAbstract:Modern enterprise applications have to satisfy increasingly stringent Quality-of-Service requirements. To ensure that a system meets its performance requirements, the ability to predict its performance under different configurations and workloads is essential. Architecture-Level performance models describe performance-relevant aspects of software Architectures and execution environments allowing to evaluate different usage profiles as well as system deployment and configuration options. However, building performance models manually requires a lot of time and effort. In this paper, we present a novel automated method for the extraction of Architecture-Level performance models of distributed component-based systems, based on monitoring data collected at run-time. The method is validated in a case study with the industry-standard SPECjEnterprise2010 Enterprise Java benchmark, a representative software system executed in a realistic environment. The obtained performance predictions match the measurements on the real system within an error margin of mostly 10-20 percent.
Sarita V. Adve - One of the best experts on this subject based on the ideXlab platform.
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DSN - Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions
37th Annual IEEE IFIP International Conference on Dependable Systems and Networks (DSN'07), 2007Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:This paper concerns the validity of a widely used method for estimating the Architecture-Level mean time to failure (MTTF) due to soft errors. The method first calculates the failure rate for an Architecture-Level component as the product of its raw error rate and an Architecture vulnerability factor (AVF). Next, the method calculates the system failure rate as the sum of the failure rates (SOFR) of all components, and the system MTTF as the reciprocal of this failure rate. Both steps make significant assumptions. We investigate the validity of the AVF+SOFR method across a large design space, using both mathematical and experimental techniques with real program traces from SPEC 2000 benchmarks and synthesized traces to simulate longer real-world workloads. We show that AVF+SOFR is valid for most of the realistic cases under current raw error rates. However, for some realistic combinations of large systems, long-running workloads with large phases, and/or large raw error rates, the MTTF calculated using AVF+SOFR shows significant-discrepancies from that using first principles. We also show that SoftArch, a previously proposed alternative method that does not make the AVF+SOFR assumptions, does not exhibit the above discrepancies.
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softarch an Architecture Level tool for modeling and analyzing soft errors
Dependable Systems and Networks, 2005Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:Soft errors are a growing concern for processor reliability. Recent work has motivated Architecture-Level studies of soft errors since the Architecture can mask many raw errors and architectural solutions can exploit workload knowledge. This paper proposes a model and tool, called SoftArch, to enable analysis of soft errors at the Architecture-Level in modern processors. SoftArch is based on a probabilistic model of the error generation and propagation process in a processor. Compared to prior Architecture-Level tools, SoftArch is more comprehensive or faster. We demonstrate the use of SoftArch for an out-of-order superscalar processor running SPEC2000 benchmarks. Our results are consistent with, but more comprehensive than, prior work, and motivate selective and dynamic Architecture-Level soft error protection mechanisms.
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Scaling of Architecture Level Soft Error Rate for Superscalar Processors
2005Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:Soft errors are a growing concern for processor reliability. Recent studies have motivated Architecture Level studies of soft errors. It has been shown that the Architecture Level has a large derating effect on the raw processor error rate. In this paper, we quantify the impact of technology scaling on the processor soft error rate, taking the Architecture Level derating effects and workload characteristics into consideration. For our evaluation, we use SoftArch to quantify the derating factor and soft error rate (SER) for different structures in a modern superscalar processor running SPEC2000 benchmarks. We compare the SERs across four different technologies ranging from 180nm to 65nm with the same microArchitecture. We find that with scaling, the derating factors for logic structures often decrease, the derating factors for storage elements remain roughly unchanged, and the FIT rate for the full processor roughly follows the trend for the raw SER of storage structures (i.e., the FIT rate.increases from 180nm to 90nm and decreases from 90nm to 65nm.
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DSN - SoftArch: an Architecture-Level tool for modeling and analyzing soft errors
2005 International Conference on Dependable Systems and Networks (DSN'05), 2005Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:Soft errors are a growing concern for processor reliability. Recent work has motivated Architecture-Level studies of soft errors since the Architecture can mask many raw errors and architectural solutions can exploit workload knowledge. This paper proposes a model and tool, called SoftArch, to enable analysis of soft errors at the Architecture-Level in modern processors. SoftArch is based on a probabilistic model of the error generation and propagation process in a processor. Compared to prior Architecture-Level tools, SoftArch is more comprehensive or faster. We demonstrate the use of SoftArch for an out-of-order superscalar processor running SPEC2000 benchmarks. Our results are consistent with, but more comprehensive than, prior work, and motivate selective and dynamic Architecture-Level soft error protection mechanisms.
Pradip Bose - One of the best experts on this subject based on the ideXlab platform.
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DSN - A Framework for Architecture-Level Lifetime Reliability Modeling
37th Annual IEEE IFIP International Conference on Dependable Systems and Networks (DSN'07), 2007Co-Authors: Jeonghee Shin, Jude A. Rivers, Victor Zyuban, Pradip BoseAbstract:This paper tackles the issue of modeling chip lifetime reliability at the Architecture Level. We propose a new and robust structure-aware lifetime reliability model at the Architecture-Level, where devices only vulnerable to failure mechanisms and the effective stress condition of these devices are taken into account for the failure rate of microArchitecture structures. In addition, we present this reliability analysis framework based on a new concept, called the FIT of reference circuit or FORC, which allows architects to quantify failure rates without having to delve into low-Level circuit- and technology-specific details of the implemented Architecture. This is done through a onetime characterization of a reference circuit needed to quantify the reference FITs for each class of modeled failure mechanisms for a given technology and implementation style. With this new reliability modeling framework, architects are empowered to proceed with Architecture-Level reliability analysis independent of technological and environmental parameters.
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DSN - Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions
37th Annual IEEE IFIP International Conference on Dependable Systems and Networks (DSN'07), 2007Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:This paper concerns the validity of a widely used method for estimating the Architecture-Level mean time to failure (MTTF) due to soft errors. The method first calculates the failure rate for an Architecture-Level component as the product of its raw error rate and an Architecture vulnerability factor (AVF). Next, the method calculates the system failure rate as the sum of the failure rates (SOFR) of all components, and the system MTTF as the reciprocal of this failure rate. Both steps make significant assumptions. We investigate the validity of the AVF+SOFR method across a large design space, using both mathematical and experimental techniques with real program traces from SPEC 2000 benchmarks and synthesized traces to simulate longer real-world workloads. We show that AVF+SOFR is valid for most of the realistic cases under current raw error rates. However, for some realistic combinations of large systems, long-running workloads with large phases, and/or large raw error rates, the MTTF calculated using AVF+SOFR shows significant-discrepancies from that using first principles. We also show that SoftArch, a previously proposed alternative method that does not make the AVF+SOFR assumptions, does not exhibit the above discrepancies.
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softarch an Architecture Level tool for modeling and analyzing soft errors
Dependable Systems and Networks, 2005Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:Soft errors are a growing concern for processor reliability. Recent work has motivated Architecture-Level studies of soft errors since the Architecture can mask many raw errors and architectural solutions can exploit workload knowledge. This paper proposes a model and tool, called SoftArch, to enable analysis of soft errors at the Architecture-Level in modern processors. SoftArch is based on a probabilistic model of the error generation and propagation process in a processor. Compared to prior Architecture-Level tools, SoftArch is more comprehensive or faster. We demonstrate the use of SoftArch for an out-of-order superscalar processor running SPEC2000 benchmarks. Our results are consistent with, but more comprehensive than, prior work, and motivate selective and dynamic Architecture-Level soft error protection mechanisms.
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Scaling of Architecture Level Soft Error Rate for Superscalar Processors
2005Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:Soft errors are a growing concern for processor reliability. Recent studies have motivated Architecture Level studies of soft errors. It has been shown that the Architecture Level has a large derating effect on the raw processor error rate. In this paper, we quantify the impact of technology scaling on the processor soft error rate, taking the Architecture Level derating effects and workload characteristics into consideration. For our evaluation, we use SoftArch to quantify the derating factor and soft error rate (SER) for different structures in a modern superscalar processor running SPEC2000 benchmarks. We compare the SERs across four different technologies ranging from 180nm to 65nm with the same microArchitecture. We find that with scaling, the derating factors for logic structures often decrease, the derating factors for storage elements remain roughly unchanged, and the FIT rate for the full processor roughly follows the trend for the raw SER of storage structures (i.e., the FIT rate.increases from 180nm to 90nm and decreases from 90nm to 65nm.
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DSN - SoftArch: an Architecture-Level tool for modeling and analyzing soft errors
2005 International Conference on Dependable Systems and Networks (DSN'05), 2005Co-Authors: Sarita V. Adve, Pradip Bose, Jude A. RiversAbstract:Soft errors are a growing concern for processor reliability. Recent work has motivated Architecture-Level studies of soft errors since the Architecture can mask many raw errors and architectural solutions can exploit workload knowledge. This paper proposes a model and tool, called SoftArch, to enable analysis of soft errors at the Architecture-Level in modern processors. SoftArch is based on a probabilistic model of the error generation and propagation process in a processor. Compared to prior Architecture-Level tools, SoftArch is more comprehensive or faster. We demonstrate the use of SoftArch for an out-of-order superscalar processor running SPEC2000 benchmarks. Our results are consistent with, but more comprehensive than, prior work, and motivate selective and dynamic Architecture-Level soft error protection mechanisms.