The Experts below are selected from a list of 32055 Experts worldwide ranked by ideXlab platform
Leonel Sousa - One of the best experts on this subject based on the ideXlab platform.
-
A Flexible Architecture for Modular Arithmetic Hardware Accelerators based on RNS
Journal of Signal Processing Systems, 2014Co-Authors: Samuel Antão, Leonel SousaAbstract:Modular Arithmetic is a building block for a variety of applications potentially supported on embedded systems. An approach to turn modular Arithmetic more efficient is to identify Algorithmic modifications that would enhance the parallelization of the target Arithmetic in order to exploit the properties of parallel devices and platforms. The Residue Number System (RNS) introduces data-level parallelism, enabling the parallelization even for Algorithms based on modular Arithmetic with several data dependencies. However, the mapping of generic Algorithms to full RNS-based implementations can be complex and the utilization of suitable hardware architectures that are scalable and adaptable to different demands is required. This paper proposes and discusses an architecture with scalability features for the parallel implementation of Algorithms relying on modular Arithmetic fully supported by the Residue Number System (RNS). The systematic mapping of a generic modular Arithmetic Algorithm to the architecture is presented. It can be applied as a high level synthesis step for an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) design flow targeting modular Arithmetic Algorithms. An implementation with the Xilinx Virtex 4 and Altera Stratix II Field Programmable Gate Array (FPGA) technologies of the modular exponentiation and Elliptic Curve (EC) point multiplication, used in the Rivest-Shamir-Adleman (RSA) and (EC) cryptographic Algorithms, suggests latency results in the same order of magnitude of the fastest hardware implementations of these operations known to date.
-
ICASSP - An RNS-based architecture targeting hardware accelerators for modular Arithmetic
2013 IEEE International Conference on Acoustics Speech and Signal Processing, 2013Co-Authors: Samuel Antão, Leonel SousaAbstract:This paper proposes and discusses an architecture with scalability features for the parallel implementation of Algorithms relying on modular Arithmetic fully supported by the Residue Number System (RNS). The systematic mapping of a generic modular Arithmetic Algorithm to the architecture is presented. It can be applied as a high level synthesis step for an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) design flow targeting modular Arithmetic Algorithms. An implementation with the Xilinx FPGA Virtex 4 technology (xc4vsx55) of modular exponentiation and Elliptic Curve (EC) point multiplication, used in the Rivest-Shamir-Adleman (RSA) and EC cryptographic Algorithms, suggests latency results in the same order of magnitude of the fastest hardware implementations of these operations known to date.
Wei Zhang - One of the best experts on this subject based on the ideXlab platform.
-
MAPP: A Modular Arithmetic Algorithm for Privacy Preserving in IoT
2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Comput, 2017Co-Authors: Mehdi Gheisari, Guojun Wang, Md Zakirul Alam Bhuiyan, Wei ZhangAbstract:High-speed Internet becomes more widely accessible, the cost of connecting devices is reducing, more devices are being created with Wi-Fi abilities and sensors are built into those devices, technology costs are cost-effective. All of these things are creating a ``storm" for the Internet of Things (IoT) era. With the emergence of the Internet of Things, connect things through internet, there are many devices that are providing data. The more devices, the more data. If these devices want to share data with the aim of achieving abstract knowledge, they need to pass through the network. Some devices provide sensitive information that can be time. We should protect these sensitive data, from unwanted disclosure that is called privacy. In other words, privacy preserving of data is one of the main problems of IoT devices, protecting sensitive data against unauthorized users when we do analysis and even transferring data. To achieve this in this paper, we propose a new method based on modular Arithmetic for privacy-preserving when IoT devices produce sensitive time label called MAPP. We applied Number Theory, Modular Arithmetic to achieve that aim. We used CupCarbon 3.0 for simulation and evaluating our proposed method. Performance evaluation shows that our proposed method has good performance from the energy consumption point of view.
-
ISPA/IUCC - MAPP: A Modular Arithmetic Algorithm for Privacy Preserving in IoT
2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Comput, 2017Co-Authors: Mehdi Gheisari, Guojun Wang, Zakirul Alam Bhuiyan, Wei ZhangAbstract:High-speed Internet becomes more widely accessible, the cost of connecting devices is reducing, more devices are being created with Wi-Fi abilities and sensors are built into those devices, technology costs are cost-effective. All of these things are creating a ``storm" for the Internet of Things (IoT) era. With the emergence of the Internet of Things, connect things through internet, there are many devices that are providing data. The more devices, the more data. If these devices want to share data with the aim of achieving abstract knowledge, they need to pass through the network. Some devices provide sensitive information that can be time. We should protect these sensitive data, from unwanted disclosure that is called privacy. In other words, privacy preserving of data is one of the main problems of IoT devices, protecting sensitive data against unauthorized users when we do analysis and even transferring data. To achieve this in this paper, we propose a new method based on modular Arithmetic for privacy-preserving when IoT devices produce sensitive time label called MAPP. We applied Number Theory, Modular Arithmetic to achieve that aim. We used CupCarbon 3.0 for simulation and evaluating our proposed method. Performance evaluation shows that our proposed method has good performance from the energy consumption point of view.
Samuel Antão - One of the best experts on this subject based on the ideXlab platform.
-
A Flexible Architecture for Modular Arithmetic Hardware Accelerators based on RNS
Journal of Signal Processing Systems, 2014Co-Authors: Samuel Antão, Leonel SousaAbstract:Modular Arithmetic is a building block for a variety of applications potentially supported on embedded systems. An approach to turn modular Arithmetic more efficient is to identify Algorithmic modifications that would enhance the parallelization of the target Arithmetic in order to exploit the properties of parallel devices and platforms. The Residue Number System (RNS) introduces data-level parallelism, enabling the parallelization even for Algorithms based on modular Arithmetic with several data dependencies. However, the mapping of generic Algorithms to full RNS-based implementations can be complex and the utilization of suitable hardware architectures that are scalable and adaptable to different demands is required. This paper proposes and discusses an architecture with scalability features for the parallel implementation of Algorithms relying on modular Arithmetic fully supported by the Residue Number System (RNS). The systematic mapping of a generic modular Arithmetic Algorithm to the architecture is presented. It can be applied as a high level synthesis step for an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) design flow targeting modular Arithmetic Algorithms. An implementation with the Xilinx Virtex 4 and Altera Stratix II Field Programmable Gate Array (FPGA) technologies of the modular exponentiation and Elliptic Curve (EC) point multiplication, used in the Rivest-Shamir-Adleman (RSA) and (EC) cryptographic Algorithms, suggests latency results in the same order of magnitude of the fastest hardware implementations of these operations known to date.
-
ICASSP - An RNS-based architecture targeting hardware accelerators for modular Arithmetic
2013 IEEE International Conference on Acoustics Speech and Signal Processing, 2013Co-Authors: Samuel Antão, Leonel SousaAbstract:This paper proposes and discusses an architecture with scalability features for the parallel implementation of Algorithms relying on modular Arithmetic fully supported by the Residue Number System (RNS). The systematic mapping of a generic modular Arithmetic Algorithm to the architecture is presented. It can be applied as a high level synthesis step for an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) design flow targeting modular Arithmetic Algorithms. An implementation with the Xilinx FPGA Virtex 4 technology (xc4vsx55) of modular exponentiation and Elliptic Curve (EC) point multiplication, used in the Rivest-Shamir-Adleman (RSA) and EC cryptographic Algorithms, suggests latency results in the same order of magnitude of the fastest hardware implementations of these operations known to date.
Antonio Peregrin - One of the best experts on this subject based on the ideXlab platform.
-
stability analysis and synthesis of multivariable fuzzy systems using interval Arithmetic
Fuzzy Sets and Systems, 2004Co-Authors: J M Andujar, J M Bravo, Antonio PeregrinAbstract:Abstract This paper deals with the design of stable rule-based fuzzy control systems. Interval analysis is applied to design a stable fuzzy Takagi–Sugeno–Kang controller using a robust condition to ensure the stability. The presented methodology starts with a state model of the plant, finds a candidate fuzzy controller and uses an interval Arithmetic Algorithm to verify the stability of closed-loop fuzzy model. It is important to emphasize the generality of the presented methodology for fuzzy controller synthesis since there are no constraints in the state vector nor in the control vector. This methodology can also be used with nonlinear plant models. In previous works we showed the applicability of the interval analysis to design a controller that ensures the stability of first order nonlinear system. In this paper, we extend the analysis and the synthesis of stable fuzzy control system to the multivariable case. An example with a fuzzy controller for a nonlinear system is presented to illustrate the design procedure.
Mehdi Gheisari - One of the best experts on this subject based on the ideXlab platform.
-
MAPP: A Modular Arithmetic Algorithm for Privacy Preserving in IoT
2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Comput, 2017Co-Authors: Mehdi Gheisari, Guojun Wang, Md Zakirul Alam Bhuiyan, Wei ZhangAbstract:High-speed Internet becomes more widely accessible, the cost of connecting devices is reducing, more devices are being created with Wi-Fi abilities and sensors are built into those devices, technology costs are cost-effective. All of these things are creating a ``storm" for the Internet of Things (IoT) era. With the emergence of the Internet of Things, connect things through internet, there are many devices that are providing data. The more devices, the more data. If these devices want to share data with the aim of achieving abstract knowledge, they need to pass through the network. Some devices provide sensitive information that can be time. We should protect these sensitive data, from unwanted disclosure that is called privacy. In other words, privacy preserving of data is one of the main problems of IoT devices, protecting sensitive data against unauthorized users when we do analysis and even transferring data. To achieve this in this paper, we propose a new method based on modular Arithmetic for privacy-preserving when IoT devices produce sensitive time label called MAPP. We applied Number Theory, Modular Arithmetic to achieve that aim. We used CupCarbon 3.0 for simulation and evaluating our proposed method. Performance evaluation shows that our proposed method has good performance from the energy consumption point of view.
-
ISPA/IUCC - MAPP: A Modular Arithmetic Algorithm for Privacy Preserving in IoT
2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Comput, 2017Co-Authors: Mehdi Gheisari, Guojun Wang, Zakirul Alam Bhuiyan, Wei ZhangAbstract:High-speed Internet becomes more widely accessible, the cost of connecting devices is reducing, more devices are being created with Wi-Fi abilities and sensors are built into those devices, technology costs are cost-effective. All of these things are creating a ``storm" for the Internet of Things (IoT) era. With the emergence of the Internet of Things, connect things through internet, there are many devices that are providing data. The more devices, the more data. If these devices want to share data with the aim of achieving abstract knowledge, they need to pass through the network. Some devices provide sensitive information that can be time. We should protect these sensitive data, from unwanted disclosure that is called privacy. In other words, privacy preserving of data is one of the main problems of IoT devices, protecting sensitive data against unauthorized users when we do analysis and even transferring data. To achieve this in this paper, we propose a new method based on modular Arithmetic for privacy-preserving when IoT devices produce sensitive time label called MAPP. We applied Number Theory, Modular Arithmetic to achieve that aim. We used CupCarbon 3.0 for simulation and evaluating our proposed method. Performance evaluation shows that our proposed method has good performance from the energy consumption point of view.