The Experts below are selected from a list of 18 Experts worldwide ranked by ideXlab platform

Senthilvel Vignesh - One of the best experts on this subject based on the ideXlab platform.

  • Design of Low Power Arithmetic Logic Unit
    2019
    Co-Authors: Senthilvel Vignesh
    Abstract:

    ALU is one of the core components of the central processing unit (CPU) of a computer. An Arithmetic logic unit (ALU) is a combinational digital electronic circuit that performs various Arithmetic operations like Addition (with carry), Increment, Subtraction (with borrow), Decrement, Two’s Complement, Multiplication, etc. and various logical operations like Bitwise AND, OR, XOR etc. and Shift operations such as Arithmetic Shift and Logical Shift. Each of these functionalities represents individual modules within an ALU. The power consumed by all these modules is the total power consumption of an ALU. When the complexity of the modules increases, ALU could take up more space in the CPU, consume more power and dissipates energy in the form of heat. This dissertation focuses on Low power ALU design without compromising its performance. Reducing the power consumption of an ALU means reducing the power consumption of individual modules. All the modules are made up of logic gates. Using low power consuming logic gates would bring down the power consumption of all modules. As Phase-I of this dissertation, low power consuming logic gates would be constructed using various existing logic styles, techniques, and devices and compared to the standard version. Phase-2 involves designing the modules using low power logic gates and optimizing the modules to a possible extent. All the circuits constructed in this work use (MOSFET) TSMC 40nm technology and simulations are done using the Cadence Virtuoso software tool.Master of Science (Electronics

Y I Qingming - One of the best experts on this subject based on the ideXlab platform.

  • 97 wavelet transform algorithm with Arithmetic Shift for hardware
    Microelectronics & Computer, 2006
    Co-Authors: Y I Qingming
    Abstract:

    Based on the searching analysis of computer, the lifting coefficients of the 97 biorthogonal wavelet filter pair of CDF are expressed in Arithmetic operation of tow Shift registers. A Arithmetic operation of Shift registers are used to replace the multiplier with complicated architecture operating on floating-point. So it is more simpler and faster, and can be implemented by ASIC easily. In the end, the analysis of some simpler algorithms and the configuration of Arithmetic Shift are given.

Shengli Xie - One of the best experts on this subject based on the ideXlab platform.

  • Arithmetic Shift method suitable for vlsi implementation to cdf 9 7 discrete wavelet transform based on lifting scheme
    International Conference on Machine Learning and Cybernetics, 2005
    Co-Authors: Qingming Yiu, Shengli Xie
    Abstract:

    For the VLSI implementation of CDF 9/7 discrete wavelet transform based on lifting scheme, a register Arithmetic Shift method is proposed. The CDF 9/7 wavelet transform with the algorithm is implemented on Matlab software platform, and is applied to Lena and calendar images. The simulation results are compared with binary representation and fraction methods. The results show that the CDF 9/7 wavelet transform with this method gains the same performance as binary representation and fraction methods and simplifies the hardware implementation. Finally, the Verilog HDL design of CDF 9/7 wavelet transform based on the register Arithmetic Shift method is implemented, and the hardware simulation wave is given.

Qingming Yiu - One of the best experts on this subject based on the ideXlab platform.

  • Arithmetic Shift method suitable for vlsi implementation to cdf 9 7 discrete wavelet transform based on lifting scheme
    International Conference on Machine Learning and Cybernetics, 2005
    Co-Authors: Qingming Yiu, Shengli Xie
    Abstract:

    For the VLSI implementation of CDF 9/7 discrete wavelet transform based on lifting scheme, a register Arithmetic Shift method is proposed. The CDF 9/7 wavelet transform with the algorithm is implemented on Matlab software platform, and is applied to Lena and calendar images. The simulation results are compared with binary representation and fraction methods. The results show that the CDF 9/7 wavelet transform with this method gains the same performance as binary representation and fraction methods and simplifies the hardware implementation. Finally, the Verilog HDL design of CDF 9/7 wavelet transform based on the register Arithmetic Shift method is implemented, and the hardware simulation wave is given.

Liu Yufeng - One of the best experts on this subject based on the ideXlab platform.

  • Design and analysis of low-power 32-bit logarithmic barrel Shifter
    'Nanyang Technological University', 2020
    Co-Authors: Liu Yufeng
    Abstract:

    With development of electronic industry, power consumption has become a priority concern for electronic products, therefore lower power design draws increasingly more attention from researchers. And data Shift is an important function unit of digital signal processors, which can be achieved by logarithmic barrel Shifter. In this dissertation, a 32-bit Logarithmic barrel Shifter with logic and Arithmetic Shift function in both right and left direction is designed in static logic, dynamic logic and sequential logic styles. The simulation and analyze of multiplexer and Logarithmic barrel Shifter are both carried out to compare power consumption and delay among different design styles. Meanwhile, the tradeoff between power consumption and delay is discussed through varying supply voltage of circuits. The process of design and simulation is carried out based on Cadence Virtuoso and TSMC’s 40nm technology is employed in this dissertation.Master of Science (Electronics