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Assertion Statement

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Wu Jian – One of the best experts on this subject based on the ideXlab platform.

    Chinese Journal of Computers, 1998
    Co-Authors: Wu Jian


    Assertion Statement in hardware description language VHDL is general-ly thought to be simulation-oriented,.thercforeit cannot or need not be synthesized,and it should be ignored or should not be supported by synthesis systems. An oppo-site viewpoint is presented in this paper: Assertion Statement in VHDL should besynthesized, the complementation of its constraint condition can be used as thedon’t-care condition in synthesis optimization. The rationality, essentiality and us-ability of synthesizing Assertion Statement are elucidated, and the synthesis meth-ods of sequential and concurrent Assertion Statements are given.

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Ashraf Salem – One of the best experts on this subject based on the ideXlab platform.

  • IDT – Automatic test pattern generation for virtual hardware model using constrained symbolic execution
    Intelligent Decision Technologies, 2015
    Co-Authors: Nahla Mohamed Mohamed, Mona Safari, Ashraf Mohamed Wahba, Ashraf Salem


    Symbolic execution is widely used for analyzing software behavior, generating test pattern, and finding bugs. However, it is not feasible for large programs. Symbolic execution attempts to explore each path of the program which result in a path explosion for large programs. This paper introduces a framework that makes the symbolic execution practical for the virtual HW models that run on QEMU platform. We describe an approach that can symbolically execute a virtual HW model to automatically generate selective test patterns. We use the constraints-based technique in order to show preferences for the generated test pattern. A native symbolic run of the program along with the constraints will generate test patterns correspond to every possible path. Our technique adds Assertion Statement into the program to indicate a specific operation mode for the device that the developer pay attention on. The symbolic engine generates test patterns that can derive the program through all feasible paths to reach the Assertion. These test patterns can be used to verify same operation mode on the associated HW RTL model.

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Peter J. Ashenden – One of the best experts on this subject based on the ideXlab platform.

  • 3 – Sequential Statements
    The Designer's Guide to VHDL, 2002
    Co-Authors: Peter J. Ashenden


    Publisher Summary
    This chapter deals with control structures that allow the selection between alternative courses of action as well as repetition of actions. One of the reasons for writing models of computer systems is to verify that a design functions correctly. Assertion Statements check that the expected conditions are met within the model. Being a sequential Statement, Assertion Statements can be included anywhere in a process body. One can write an Assertion Statement with either a report clause or a severity clause, or both. Assertion Statements are also used for checking the timing constraints that apply to a model.

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