The Experts below are selected from a list of 453 Experts worldwide ranked by ideXlab platform
Dana S. Henry - One of the best experts on this subject based on the ideXlab platform.
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Adding Fast Interrupts to Superscalar Processors
2005Co-Authors: Dana S. HenryAbstract:The hardware cost of taking an Interrupt is increasing as processors become more superscalar. Using FLIP, an aggressively superscalar processor which we have designed and tested in Verilog, we demonstrate that Interrupts can be fast and inexpensive. We trace individual signals through FLIP’s pipeline stages to show that fast Interrupts require negligible new hardware. Except for linkage information, Interrupts reuse existing branch mechanisms. An Asynchronous Interrupt acts as an immediate jump instruction, while a synchronous Interrupt acts as a mispredicted branch. Although we concentrate on user-level Interrupts, we show that kernel-level Interrupts can be handled identically with the addition of protection mode bits to identify the protection mode of every outstanding instruction. In blending fast Interrupts into the superscalar processor, we address two new problems. The first problem arises from fast synchronous Interrupts. Because most instructions can cause an Interrupt, the processor must be able to revert to its state prior to most instructions, not just mispredicted branches. This ubiquitousness of reversion leads us to design a new renaming data structure. Our renaming data structure can revert to the state prior to any outstanding instruction by updating a single pointer. The entire structure consists of the outstanding renaming bindings plus a simple scan circuit to look up the latest binding. The second problem arises from the interaction of mispredicted branches and Asynchronous Interrupts. An Asynchronous Interrupt can sometimes vanish if a branch which dynamically precedes the Interrupt handler mispredicts. We offer a simple solution in which the processor remembers an outstanding Interrupt and replays the Interrupt in case of a preceding misprediction.
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Adding Fast Interrupts to Superscalar Processors
1994Co-Authors: Dana Henry, Dana S. HenryAbstract:The hardware cost of taking an Interrupt is increasing as processors become more superscalar. Using FLIP, an aggressively superscalar processor which we have designed and tested in Verilog, we demonstrate that Interrupts can be fast and inexpensive. We trace individual signals through FLIP's pipeline stages to show that fast Interrupts require negligible new hardware. Except for linkage information, Interrupts reuse existing branch mechanisms. An Asynchronous Interrupt acts as an immediate jump instruction, while a synchronous Interrupt acts as a mispredicted branch. Although we concentrate on user-level Interrupts, we show that kernel-level Interrupts can be handled identically with the addition of protection mode bits to identify the protection mode of every outstanding instruction. In blending fast Interrupts into the superscalar processor, we address two new problems. The first problem arises from fast synchronous Interrupts. Because most instructions can cause an Interrupt, the pr..
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Abstract Adding Fast Interrupts to Superscalar Processors
1994Co-Authors: Dana Henry, Dana S. HenryAbstract:The hardware cost of taking an Interrupt is increasing as processors become more superscalar. Using FLIP, an aggressively superscalar processor which we have designed and tested in Verilog, we demonstrate that Interrupts can be fast and inexpensive. We trace individual signals through FLIP’s pipeline stages to show that fast Interrupts require negligible new hardware. Except for linkage information, Interrupts reuse existing branch mechanisms. An Asynchronous Interrupt acts as an immediate jump instruction, while a synchronous Interrupt acts as a mispredicted branch. Although we concentrate on user-level Interrupts, we show that kernel-level Interrupts can be handled identically with the addition of protection mode bits to identify the protection mode of every outstanding instruction. In blending fast Interrupts into the superscalar processor, we address two new problems. The first problem arises from fast synchronous Interrupts. Because most instructions can cause an Interrupt, the processor must be able to revert to its state prior to most instructions, not just mispredicted branches. This ubiquitousness of reversion leads us to design a new renaming data structure. Our renaming data structure can revert to the state prior to any outstanding instruction by updating a single pointer. The entire structure consists of the outstanding renaming bindings plu
Bjorn Franke - One of the best experts on this subject based on the ideXlab platform.
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efficient Asynchronous Interrupt handling in a full system instruction set simulator
Languages Compilers and Tools for Embedded Systems, 2016Co-Authors: Tom Spink, Harry Wagstaff, Bjorn FrankeAbstract:Instruction set simulators (ISS) have many uses in embedded software and hardware development and are typically based on dynamic binary translation (DBT), where frequently executed regions of guest instructions are compiled into host instructions using a just-in-time (JIT) compiler. Full-system simulation, which necessitates handling of Asynchronous Interrupts from e.g. timers and I/O devices, complicates matters as control flow is Interrupted unpredictably and diverted from the current region of code. In this paper we present a novel scheme for handling of Asynchronous Interrupts, which integrates seamlessly into a region-based dynamic binary translator. We first show that our scheme is correct, i.e. Interrupt handling is not deferred indefinitely, even in the presence of code regions comprising control flow loops. We demonstrate that our new Interrupt handling scheme is efficient as we minimise the number of inserted checks. Interrupt handlers are also presented to the JIT compiler and compiled to native code, further enhancing the performance of our system. We have evaluated our scheme in an ARM simulator using a region-based JIT compilation strategy. We demonstrate that our solution reduces the number of dynamic Interrupt checks by 73%, reduces Interrupt service latency by 26% and improves throughput of an I/O bound workload by 7%, over traditional per-block schemes.
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LCTES - Efficient Asynchronous Interrupt handling in a full-system instruction set simulator
Proceedings of the 17th ACM SIGPLAN SIGBED Conference on Languages Compilers Tools and Theory for Embedded Systems - LCTES 2016, 2016Co-Authors: Tom Spink, Harry Wagstaff, Bjorn FrankeAbstract:Instruction set simulators (ISS) have many uses in embedded software and hardware development and are typically based on dynamic binary translation (DBT), where frequently executed regions of guest instructions are compiled into host instructions using a just-in-time (JIT) compiler. Full-system simulation, which necessitates handling of Asynchronous Interrupts from e.g. timers and I/O devices, complicates matters as control flow is Interrupted unpredictably and diverted from the current region of code. In this paper we present a novel scheme for handling of Asynchronous Interrupts, which integrates seamlessly into a region-based dynamic binary translator. We first show that our scheme is correct, i.e. Interrupt handling is not deferred indefinitely, even in the presence of code regions comprising control flow loops. We demonstrate that our new Interrupt handling scheme is efficient as we minimise the number of inserted checks. Interrupt handlers are also presented to the JIT compiler and compiled to native code, further enhancing the performance of our system. We have evaluated our scheme in an ARM simulator using a region-based JIT compilation strategy. We demonstrate that our solution reduces the number of dynamic Interrupt checks by 73%, reduces Interrupt service latency by 26% and improves throughput of an I/O bound workload by 7%, over traditional per-block schemes.
Tom Spink - One of the best experts on this subject based on the ideXlab platform.
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efficient Asynchronous Interrupt handling in a full system instruction set simulator
Languages Compilers and Tools for Embedded Systems, 2016Co-Authors: Tom Spink, Harry Wagstaff, Bjorn FrankeAbstract:Instruction set simulators (ISS) have many uses in embedded software and hardware development and are typically based on dynamic binary translation (DBT), where frequently executed regions of guest instructions are compiled into host instructions using a just-in-time (JIT) compiler. Full-system simulation, which necessitates handling of Asynchronous Interrupts from e.g. timers and I/O devices, complicates matters as control flow is Interrupted unpredictably and diverted from the current region of code. In this paper we present a novel scheme for handling of Asynchronous Interrupts, which integrates seamlessly into a region-based dynamic binary translator. We first show that our scheme is correct, i.e. Interrupt handling is not deferred indefinitely, even in the presence of code regions comprising control flow loops. We demonstrate that our new Interrupt handling scheme is efficient as we minimise the number of inserted checks. Interrupt handlers are also presented to the JIT compiler and compiled to native code, further enhancing the performance of our system. We have evaluated our scheme in an ARM simulator using a region-based JIT compilation strategy. We demonstrate that our solution reduces the number of dynamic Interrupt checks by 73%, reduces Interrupt service latency by 26% and improves throughput of an I/O bound workload by 7%, over traditional per-block schemes.
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LCTES - Efficient Asynchronous Interrupt handling in a full-system instruction set simulator
Proceedings of the 17th ACM SIGPLAN SIGBED Conference on Languages Compilers Tools and Theory for Embedded Systems - LCTES 2016, 2016Co-Authors: Tom Spink, Harry Wagstaff, Bjorn FrankeAbstract:Instruction set simulators (ISS) have many uses in embedded software and hardware development and are typically based on dynamic binary translation (DBT), where frequently executed regions of guest instructions are compiled into host instructions using a just-in-time (JIT) compiler. Full-system simulation, which necessitates handling of Asynchronous Interrupts from e.g. timers and I/O devices, complicates matters as control flow is Interrupted unpredictably and diverted from the current region of code. In this paper we present a novel scheme for handling of Asynchronous Interrupts, which integrates seamlessly into a region-based dynamic binary translator. We first show that our scheme is correct, i.e. Interrupt handling is not deferred indefinitely, even in the presence of code regions comprising control flow loops. We demonstrate that our new Interrupt handling scheme is efficient as we minimise the number of inserted checks. Interrupt handlers are also presented to the JIT compiler and compiled to native code, further enhancing the performance of our system. We have evaluated our scheme in an ARM simulator using a region-based JIT compilation strategy. We demonstrate that our solution reduces the number of dynamic Interrupt checks by 73%, reduces Interrupt service latency by 26% and improves throughput of an I/O bound workload by 7%, over traditional per-block schemes.
Dana Henry - One of the best experts on this subject based on the ideXlab platform.
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Adding Fast Interrupts to Superscalar Processors
1994Co-Authors: Dana Henry, Dana S. HenryAbstract:The hardware cost of taking an Interrupt is increasing as processors become more superscalar. Using FLIP, an aggressively superscalar processor which we have designed and tested in Verilog, we demonstrate that Interrupts can be fast and inexpensive. We trace individual signals through FLIP's pipeline stages to show that fast Interrupts require negligible new hardware. Except for linkage information, Interrupts reuse existing branch mechanisms. An Asynchronous Interrupt acts as an immediate jump instruction, while a synchronous Interrupt acts as a mispredicted branch. Although we concentrate on user-level Interrupts, we show that kernel-level Interrupts can be handled identically with the addition of protection mode bits to identify the protection mode of every outstanding instruction. In blending fast Interrupts into the superscalar processor, we address two new problems. The first problem arises from fast synchronous Interrupts. Because most instructions can cause an Interrupt, the pr..
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Abstract Adding Fast Interrupts to Superscalar Processors
1994Co-Authors: Dana Henry, Dana S. HenryAbstract:The hardware cost of taking an Interrupt is increasing as processors become more superscalar. Using FLIP, an aggressively superscalar processor which we have designed and tested in Verilog, we demonstrate that Interrupts can be fast and inexpensive. We trace individual signals through FLIP’s pipeline stages to show that fast Interrupts require negligible new hardware. Except for linkage information, Interrupts reuse existing branch mechanisms. An Asynchronous Interrupt acts as an immediate jump instruction, while a synchronous Interrupt acts as a mispredicted branch. Although we concentrate on user-level Interrupts, we show that kernel-level Interrupts can be handled identically with the addition of protection mode bits to identify the protection mode of every outstanding instruction. In blending fast Interrupts into the superscalar processor, we address two new problems. The first problem arises from fast synchronous Interrupts. Because most instructions can cause an Interrupt, the processor must be able to revert to its state prior to most instructions, not just mispredicted branches. This ubiquitousness of reversion leads us to design a new renaming data structure. Our renaming data structure can revert to the state prior to any outstanding instruction by updating a single pointer. The entire structure consists of the outstanding renaming bindings plu
Frankebjörn - One of the best experts on this subject based on the ideXlab platform.
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Efficient Asynchronous Interrupt handling in a full-system instruction set simulator
Sigplan Notices, 2016Co-Authors: Spinktom, Wagstaffharry, FrankebjörnAbstract:Instruction set simulators (ISS) have many uses in embedded software and hardware development and are typically based on dynamic binary translation (DBT), where frequently executed regions of guest...