The Experts below are selected from a list of 34107 Experts worldwide ranked by ideXlab platform
Saibal Mukhopadhyay - One of the best experts on this subject based on the ideXlab platform.
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improved power em side channel Attack Resistance of 128 bit aes engines with random fast voltage dithering
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Arvind Singh, Monodeep Kar, Anand Rajan, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper demonstrates the improved power and electromagnetic (EM) side-channel Attack (SCA) Resistance of 128-bit Advanced Encryption Standard (AES) engines in 130-nm CMOS using random fast voltage dithering (RFVD) enabled by integrated voltage regulator (IVR) with the bond-wire inductors and an on-chip all-digital clock modulation (ADCM) circuit. RFVD scheme transforms the current signatures with random variations in AES input supply while adding random shifts in the clock edges in the presence of global and local supply noises. The measured power signatures at the supply node of the AES engines show upto 37 $\times $ reduction in peak for higher order test vector leakage assessment (TVLA) metric and upto 692 $\times $ increase in minimum traces required to disclose (MTD) the secret encryption key with correlation power analysis (CPA). Similarly, SCA on the measured EM signatures from the chip demonstrates a reduction of upto 11.3 $\times $ in TVLA peak and upto 37 $\times $ increase in correlation EM analysis (CEMA) MTD.
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improved power side channel Attack Resistance of a 128 bit aes engine with random fast voltage dithering
European Solid-State Circuits Conference, 2017Co-Authors: Arvind Singh, Monodeep Kar, Anand Rajan, Sanu Mathew, Saibal MukhopadhyayAbstract:The paper demonstrates improved power side channel Attack (PSCA) Resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation power analysis (CPA) Attacks even after 500,000 encryption traces.
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ESSCIRC - Improved power side channel Attack Resistance of a 128-bit AES engine with random fast voltage dithering
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017Co-Authors: Arvind Singh, Anand Rajan, Vivek De, Sanu K. Mathew, Saibal MukhopadhyayAbstract:The paper demonstrates improved power side channel Attack (PSCA) Resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation power analysis (CPA) Attacks even after 500,000 encryption traces.
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what does ultra low power requirements mean for side channel secure cryptography
International Conference on Computer Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-Attack resistant encryption engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel Resistance. On one hand, low-power encryption architecture can be more vulnerable to power-Attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-Attack Resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.
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ICCD - What does ultra low power requirements mean for side-channel secure cryptography?
2016 IEEE 34th International Conference on Computer Design (ICCD), 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-Attack resistant encryption engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel Resistance. On one hand, low-power encryption architecture can be more vulnerable to power-Attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-Attack Resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.
Arvind Singh - One of the best experts on this subject based on the ideXlab platform.
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improved power em side channel Attack Resistance of 128 bit aes engines with random fast voltage dithering
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Arvind Singh, Monodeep Kar, Anand Rajan, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper demonstrates the improved power and electromagnetic (EM) side-channel Attack (SCA) Resistance of 128-bit Advanced Encryption Standard (AES) engines in 130-nm CMOS using random fast voltage dithering (RFVD) enabled by integrated voltage regulator (IVR) with the bond-wire inductors and an on-chip all-digital clock modulation (ADCM) circuit. RFVD scheme transforms the current signatures with random variations in AES input supply while adding random shifts in the clock edges in the presence of global and local supply noises. The measured power signatures at the supply node of the AES engines show upto 37 $\times $ reduction in peak for higher order test vector leakage assessment (TVLA) metric and upto 692 $\times $ increase in minimum traces required to disclose (MTD) the secret encryption key with correlation power analysis (CPA). Similarly, SCA on the measured EM signatures from the chip demonstrates a reduction of upto 11.3 $\times $ in TVLA peak and upto 37 $\times $ increase in correlation EM analysis (CEMA) MTD.
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improved power side channel Attack Resistance of a 128 bit aes engine with random fast voltage dithering
European Solid-State Circuits Conference, 2017Co-Authors: Arvind Singh, Monodeep Kar, Anand Rajan, Sanu Mathew, Saibal MukhopadhyayAbstract:The paper demonstrates improved power side channel Attack (PSCA) Resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation power analysis (CPA) Attacks even after 500,000 encryption traces.
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ESSCIRC - Improved power side channel Attack Resistance of a 128-bit AES engine with random fast voltage dithering
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017Co-Authors: Arvind Singh, Anand Rajan, Vivek De, Sanu K. Mathew, Saibal MukhopadhyayAbstract:The paper demonstrates improved power side channel Attack (PSCA) Resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation power analysis (CPA) Attacks even after 500,000 encryption traces.
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what does ultra low power requirements mean for side channel secure cryptography
International Conference on Computer Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-Attack resistant encryption engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel Resistance. On one hand, low-power encryption architecture can be more vulnerable to power-Attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-Attack Resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.
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ICCD - What does ultra low power requirements mean for side-channel secure cryptography?
2016 IEEE 34th International Conference on Computer Design (ICCD), 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-Attack resistant encryption engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel Resistance. On one hand, low-power encryption architecture can be more vulnerable to power-Attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-Attack Resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.
Monodeep Kar - One of the best experts on this subject based on the ideXlab platform.
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improved power em side channel Attack Resistance of 128 bit aes engines with random fast voltage dithering
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Arvind Singh, Monodeep Kar, Anand Rajan, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper demonstrates the improved power and electromagnetic (EM) side-channel Attack (SCA) Resistance of 128-bit Advanced Encryption Standard (AES) engines in 130-nm CMOS using random fast voltage dithering (RFVD) enabled by integrated voltage regulator (IVR) with the bond-wire inductors and an on-chip all-digital clock modulation (ADCM) circuit. RFVD scheme transforms the current signatures with random variations in AES input supply while adding random shifts in the clock edges in the presence of global and local supply noises. The measured power signatures at the supply node of the AES engines show upto 37 $\times $ reduction in peak for higher order test vector leakage assessment (TVLA) metric and upto 692 $\times $ increase in minimum traces required to disclose (MTD) the secret encryption key with correlation power analysis (CPA). Similarly, SCA on the measured EM signatures from the chip demonstrates a reduction of upto 11.3 $\times $ in TVLA peak and upto 37 $\times $ increase in correlation EM analysis (CEMA) MTD.
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improved power side channel Attack Resistance of a 128 bit aes engine with random fast voltage dithering
European Solid-State Circuits Conference, 2017Co-Authors: Arvind Singh, Monodeep Kar, Anand Rajan, Sanu Mathew, Saibal MukhopadhyayAbstract:The paper demonstrates improved power side channel Attack (PSCA) Resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation power analysis (CPA) Attacks even after 500,000 encryption traces.
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what does ultra low power requirements mean for side channel secure cryptography
International Conference on Computer Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-Attack resistant encryption engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel Resistance. On one hand, low-power encryption architecture can be more vulnerable to power-Attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-Attack Resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.
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ICCD - What does ultra low power requirements mean for side-channel secure cryptography?
2016 IEEE 34th International Conference on Computer Design (ICCD), 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-Attack resistant encryption engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel Resistance. On one hand, low-power encryption architecture can be more vulnerable to power-Attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-Attack Resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.
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exploring power Attack protection of resource constrained encryption engines using integrated low drop out regulators
International Symposium on Low Power Electronics and Design, 2015Co-Authors: Arvind Singh, Monodeep Kar, Saibal MukhopadhyayAbstract:The power Attack protection of encryption engines often comes at the expense of area, power, and/or performance overheads making the design of a low-power and compact but secure encryption engine challenging. This paper explores the feasibility of using an on-chip low dropout regulator (LDO) as a countermeasure to power Attack of low-power and compact encryption engine. We design an area minimized implementation of Advanced Encryption Standard (AES) using predictive 45nm node and show that lightweight implementations are more susceptible to power Attack. Using behavioral modeling, we show that an on-chip LDO can enhance power Attack Resistance of this compact AES engine; however, the tradeoff between LDO performance and power Attack protection is essential. Our analysis shows that LDO can increase power Attack Resistance of the compact AES by >800X with marginal area (1.4%) and power (5%) overheads.
Haeseung Lee - One of the best experts on this subject based on the ideXlab platform.
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s2adc a 12 bit 1 25 ms s secure sar adc with power side channel Attack Resistance
IEEE Journal of Solid-state Circuits, 2021Co-Authors: Taehoon Jeong, Anantha P Chandrakasan, Haeseung LeeAbstract:When an ADC is converting a confidential analog signal into digital codes, it may expose a critical hardware security loophole. By exploiting the strong correlation between the ADC digital output codes and the ADC supply current waveforms, an Attacker can perform an ADC power side-channel Attack (PSA) to steal the sensitive A/D conversion results by tapping into the power supply of the ADC. In this regard, this article demonstrates two neural-network-based successive approximation register (SAR) ADC PSA methods and a 12-bit, 1.25-MS/s prototype SAR ADC with current-equalizer-based PSA protection. The first ADC PSA method employs multi-layer perceptron networks (MLP-PSA), while the second ADC PSA method uses convolutional neural networks (CNN-PSA). With the protection disabled, both MLP-PSA and CNN-PSA extract the A/D conversion results from the ADC supply current waveforms with >99% bit-wise accuracy. With the protection enabled, strong PSA-Resistance against MLP-PSA is demonstrated. The same SAR ADC exhibits weaker PSA-Resistance against CNN-PSA but generally provides significant protection of A/D conversion results.
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s2adc a 12 bit 1 25ms s secure sar adc with power side channel Attack Resistance
Custom Integrated Circuits Conference, 2020Co-Authors: Taehoon Jeong, Anantha P Chandrakasan, Haeseung LeeAbstract:This paper presents a neural-network-based SAR ADC power side-channel Attack (PSA) method and a 12-bit, 1.25MS/s secure SAR ADC whose current equalizers protect the ADC from PSA. A prototype SAR ADC was fabricated in 65nm CMOS to demonstrate the proposed concepts. Without PSA protection, the proposed PSA method decoded the power supply current waveforms of the prototype ADC into the corresponding A/D converter output bits with >99% bit-wise accuracy except for the LSB. With PSA protection, the prototype ADC demonstrated high Resistance to the proposed PSA method, showing significant drop in bit-wise accuracy.
Anand Rajan - One of the best experts on this subject based on the ideXlab platform.
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improved power em side channel Attack Resistance of 128 bit aes engines with random fast voltage dithering
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Arvind Singh, Monodeep Kar, Anand Rajan, Sanu Mathew, Saibal MukhopadhyayAbstract:This paper demonstrates the improved power and electromagnetic (EM) side-channel Attack (SCA) Resistance of 128-bit Advanced Encryption Standard (AES) engines in 130-nm CMOS using random fast voltage dithering (RFVD) enabled by integrated voltage regulator (IVR) with the bond-wire inductors and an on-chip all-digital clock modulation (ADCM) circuit. RFVD scheme transforms the current signatures with random variations in AES input supply while adding random shifts in the clock edges in the presence of global and local supply noises. The measured power signatures at the supply node of the AES engines show upto 37 $\times $ reduction in peak for higher order test vector leakage assessment (TVLA) metric and upto 692 $\times $ increase in minimum traces required to disclose (MTD) the secret encryption key with correlation power analysis (CPA). Similarly, SCA on the measured EM signatures from the chip demonstrates a reduction of upto 11.3 $\times $ in TVLA peak and upto 37 $\times $ increase in correlation EM analysis (CEMA) MTD.
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improved power side channel Attack Resistance of a 128 bit aes engine with random fast voltage dithering
European Solid-State Circuits Conference, 2017Co-Authors: Arvind Singh, Monodeep Kar, Anand Rajan, Sanu Mathew, Saibal MukhopadhyayAbstract:The paper demonstrates improved power side channel Attack (PSCA) Resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation power analysis (CPA) Attacks even after 500,000 encryption traces.
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ESSCIRC - Improved power side channel Attack Resistance of a 128-bit AES engine with random fast voltage dithering
ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017Co-Authors: Arvind Singh, Anand Rajan, Vivek De, Sanu K. Mathew, Saibal MukhopadhyayAbstract:The paper demonstrates improved power side channel Attack (PSCA) Resistance of a 128-bit AES engine in 130nm CMOS using random fast voltage dithering (RFVD) enabled by integrated inductive voltage regulator (IVR) and all-digital clock modulation (ADCM). The measured power signatures at AES and IVR supply nodes show 9× reduction in peak test vector leakage assessment (TVLA) metric while also protecting encryption keys from correlation power analysis (CPA) Attacks even after 500,000 encryption traces.
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what does ultra low power requirements mean for side channel secure cryptography
International Conference on Computer Design, 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-Attack resistant encryption engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel Resistance. On one hand, low-power encryption architecture can be more vulnerable to power-Attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-Attack Resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.
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ICCD - What does ultra low power requirements mean for side-channel secure cryptography?
2016 IEEE 34th International Conference on Computer Design (ICCD), 2016Co-Authors: Monodeep Kar, Anand Rajan, Vivek De, Arvind Singh, Saibal MukhopadhyayAbstract:The design of low power and side-channel-Attack resistant encryption engine is a key challenge to enhance security of resource-constrained platforms. This paper present case studies to show that the low-power requirement is a challenge as well as an opportunity for improving side-channel Resistance. On one hand, low-power encryption architecture can be more vulnerable to power-Attack; and the countermeasures comes with significant overhead. However, on the other hand, low-power circuit techniques such as integrated voltage regulation or adaptive clocking can also be exploited to improve power-Attack Resistance. The analysis shows the need for future research on low-power and side-channel secure cryptography.