The Experts below are selected from a list of 651 Experts worldwide ranked by ideXlab platform
Newe Thomas - One of the best experts on this subject based on the ideXlab platform.
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An FPGA based reconfigurable IPSec ESP core suitable for IoT applications
'Institute of Electrical and Electronics Engineers (IEEE)', 2017Co-Authors: Rao Muzaffar, Coleman Joseph, Newe ThomasAbstract:peer-reviewedThis work implements an FPGA (Field Programmable Gate Array) based reconfigurable IPSec ESP core. The IPSec protocol, developed by the IETF (Internet Engineering Task Force) in 1998, is a popular solution to facilitate protection of the data being transferred at the IP layer. IPSec ESP is one of the two main IPSec protocols (AH: Authentication Header and ESP: Encapsulation Security Payload). IPSec ESP is used to provide data confidentiality security services with Authenticity (optional). Implementation of the IPSec is a computing intensive work, that's why hardware implementation of IPSec is a best solution. Here, to design IPSec ESP core an encryption algorithm AES is used. Proposed design also supports ESP-tunnel and ESP-transport mode of operation. This core is tested by applying default length of 576 bytes for an IPv4 datagram and results are reported on Virtex-5 and Virtex-6 FPGAs. The proposed IPSec ESP core can be used to provide data confidentiality security to IoT applications.ACCEPTEDpeer-reviewe
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An FPGA based reconfigurable IPSec ESP core suitable for IoT applications
IEEE Computer Society, 2016Co-Authors: Rao Muzaffar, Coleman Joseph, Newe ThomasAbstract:This work implements an FPGA (Field Programmable Gate Array) based reconfigurable IPSec ESP core. The IPSec protocol, developed by the IETF (Internet Engineering Task Force) in 1998, is a popular solution to facilitate protection of the data being transferred at the IP layer. IPSec ESP is one of the two main IPSec protocols (AH: Authentication Header and ESP: Encapsulation Security Payload). IPSec ESP is used to provide data confidentiality security services with Authenticity (optional). Implementation of the IPSec is a computing intensive work, that\u27s why hardware implementation of IPSec is a best solution. Here, to design IPSec ESP core an encryption algorithm AES is used. Proposed design also supports ESP-tunnel and ESP-transport mode of operation. This core is tested by applying default length of 576 bytes for an IPv4 datagram and results are reported on Virtex-5 and Virtex-6 FPGAs. The proposed IPSec ESP core can be used to provide data confidentiality security to IoT applications.ACCEPTEDpeer-reviewe
Rao Muzaffar - One of the best experts on this subject based on the ideXlab platform.
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An FPGA based reconfigurable IPSec ESP core suitable for IoT applications
'Institute of Electrical and Electronics Engineers (IEEE)', 2017Co-Authors: Rao Muzaffar, Coleman Joseph, Newe ThomasAbstract:peer-reviewedThis work implements an FPGA (Field Programmable Gate Array) based reconfigurable IPSec ESP core. The IPSec protocol, developed by the IETF (Internet Engineering Task Force) in 1998, is a popular solution to facilitate protection of the data being transferred at the IP layer. IPSec ESP is one of the two main IPSec protocols (AH: Authentication Header and ESP: Encapsulation Security Payload). IPSec ESP is used to provide data confidentiality security services with Authenticity (optional). Implementation of the IPSec is a computing intensive work, that's why hardware implementation of IPSec is a best solution. Here, to design IPSec ESP core an encryption algorithm AES is used. Proposed design also supports ESP-tunnel and ESP-transport mode of operation. This core is tested by applying default length of 576 bytes for an IPv4 datagram and results are reported on Virtex-5 and Virtex-6 FPGAs. The proposed IPSec ESP core can be used to provide data confidentiality security to IoT applications.ACCEPTEDpeer-reviewe
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An FPGA based reconfigurable IPSec ESP core suitable for IoT applications
IEEE Computer Society, 2016Co-Authors: Rao Muzaffar, Coleman Joseph, Newe ThomasAbstract:This work implements an FPGA (Field Programmable Gate Array) based reconfigurable IPSec ESP core. The IPSec protocol, developed by the IETF (Internet Engineering Task Force) in 1998, is a popular solution to facilitate protection of the data being transferred at the IP layer. IPSec ESP is one of the two main IPSec protocols (AH: Authentication Header and ESP: Encapsulation Security Payload). IPSec ESP is used to provide data confidentiality security services with Authenticity (optional). Implementation of the IPSec is a computing intensive work, that\u27s why hardware implementation of IPSec is a best solution. Here, to design IPSec ESP core an encryption algorithm AES is used. Proposed design also supports ESP-tunnel and ESP-transport mode of operation. This core is tested by applying default length of 576 bytes for an IPv4 datagram and results are reported on Virtex-5 and Virtex-6 FPGAs. The proposed IPSec ESP core can be used to provide data confidentiality security to IoT applications.ACCEPTEDpeer-reviewe
Yaopo Wang - One of the best experts on this subject based on the ideXlab platform.
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fpga Authentication Header ah implementation for internet appliances
Pacific Rim International Symposium on Dependable Computing, 2005Co-Authors: Changchun Cheng, Weiming Chen, Hanchieh Chao, Yaopo WangAbstract:Data integrity assurance and data origin Authentication are essential security services in financial transactions, electronic commerce, electronic mail, software distribution, data storage and so on. Nowadays, consumer electronics has been shifted toward Internet or intelligent appliances (IA) with network capability to exchange information through Internet. Therefore, a hardware based security mechanism is essential to be combined into the IA so that security and performance can be both preserved. In the Internet protocol security (IPSec) mechanism, the Authentication Header (AH) is an important portion. The two Authentication algorithms specified for AH are MD5 and SHA-1 which have been implemented and evaluated in FPGA. With the proposed enhanced (register usage and concurrent statement) operation core design, a 6% improvement for slice utilization plus 24% more throughput for MD5 are obtained comparing to the previous one.
Coleman Joseph - One of the best experts on this subject based on the ideXlab platform.
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An FPGA based reconfigurable IPSec ESP core suitable for IoT applications
'Institute of Electrical and Electronics Engineers (IEEE)', 2017Co-Authors: Rao Muzaffar, Coleman Joseph, Newe ThomasAbstract:peer-reviewedThis work implements an FPGA (Field Programmable Gate Array) based reconfigurable IPSec ESP core. The IPSec protocol, developed by the IETF (Internet Engineering Task Force) in 1998, is a popular solution to facilitate protection of the data being transferred at the IP layer. IPSec ESP is one of the two main IPSec protocols (AH: Authentication Header and ESP: Encapsulation Security Payload). IPSec ESP is used to provide data confidentiality security services with Authenticity (optional). Implementation of the IPSec is a computing intensive work, that's why hardware implementation of IPSec is a best solution. Here, to design IPSec ESP core an encryption algorithm AES is used. Proposed design also supports ESP-tunnel and ESP-transport mode of operation. This core is tested by applying default length of 576 bytes for an IPv4 datagram and results are reported on Virtex-5 and Virtex-6 FPGAs. The proposed IPSec ESP core can be used to provide data confidentiality security to IoT applications.ACCEPTEDpeer-reviewe
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An FPGA based reconfigurable IPSec ESP core suitable for IoT applications
IEEE Computer Society, 2016Co-Authors: Rao Muzaffar, Coleman Joseph, Newe ThomasAbstract:This work implements an FPGA (Field Programmable Gate Array) based reconfigurable IPSec ESP core. The IPSec protocol, developed by the IETF (Internet Engineering Task Force) in 1998, is a popular solution to facilitate protection of the data being transferred at the IP layer. IPSec ESP is one of the two main IPSec protocols (AH: Authentication Header and ESP: Encapsulation Security Payload). IPSec ESP is used to provide data confidentiality security services with Authenticity (optional). Implementation of the IPSec is a computing intensive work, that\u27s why hardware implementation of IPSec is a best solution. Here, to design IPSec ESP core an encryption algorithm AES is used. Proposed design also supports ESP-tunnel and ESP-transport mode of operation. This core is tested by applying default length of 576 bytes for an IPv4 datagram and results are reported on Virtex-5 and Virtex-6 FPGAs. The proposed IPSec ESP core can be used to provide data confidentiality security to IoT applications.ACCEPTEDpeer-reviewe
Jenspeter Kaps - One of the best experts on this subject based on the ideXlab platform.
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Efficient Hardware Accelerator for IPSec based on Partial Reconfiguration on Xilinx FPGAs
2014Co-Authors: Ahmad Salman, Marcin Rogawski, Jenspeter KapsAbstract:Abstract—In this paper we present a practical low-end embed-ded system solution for Internet Protocol Security (IPSec) imple-mented on the smallest Xilinx Field Programmable Gate Array (FPGA) device in the Virtex 4 family. The proposed solution supports the three main IPSec protocols: Encapsulating Security Payload (ESP), Authentication Header (AH) and Internet Key Exchange (IKE). This system uses efficiently hardware-software co-design and partial reconfiguration techniques. Thanks to utilization of both methods we were able to save a significant portion of hardware resources with a relatively small penalty in terms of performance. In this work we propose a division of the basic mechanisms of IPSec protocols, namely cryptographic algorithms and their modes of operation to be implemented either in software or hardware. Through this, we were able to combine the high performance offered by a hardware solution with the flexibility of a software implementation. We show that a typical IPSec protocol configuration can be combined with Partial Reconfiguration techniques in order to efficiently utilize hardware resources. Index Terms—Partial reconfiguration; IPSec; Xilinx FPGA I
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efficient hardware accelerator for ipsec based on partial reconfiguration on xilinx fpgas
Reconfigurable Computing and FPGAs, 2011Co-Authors: Ahmad Salman, Marcin Rogawski, Jenspeter KapsAbstract:In this paper we present a practical low-end embedded system solution for Internet Protocol Security (IPSec) implemented on the smallest Xilinx Field Programmable Gate Array (FPGA) device in the Virtex 4 family. The proposed solution supports the three main IPSec protocols: Encapsulating Security Payload (ESP), Authentication Header (AH) and Internet Key Exchange (IKE). This system uses efficiently hardware-software co-design and partial reconfiguration techniques. Thanks to utilization of both methods we were able to save a significant portion of hardware resources with a relatively small penalty in terms of performance. In this work we propose a division of the basic mechanisms of IPSec protocols, namely cryptographic algorithms and their modes of operation to be implemented either in software or hardware. Through this, we were able to combine the high performance offered by a hardware solution with the flexibility of a software implementation. We show that a typical IPSec protocol configuration can be combined with Partial Reconfiguration techniques in order to efficiently utilize hardware resources.
