The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Lishiuan Peh - One of the best experts on this subject based on the ideXlab platform.
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spectrum a software defined predictable many core architecture for lte 5g Baseband Processing
ACM Transactions in Embedded Computing Systems, 2020Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Lishiuan PehAbstract:Wireless communication standards such as Long-term Evolution (LTE) are rapidly changing to support the high data-rate of wireless devices. The physical layer Baseband Processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing basestation transceivers utilize customized DSP cores or fixed-function hardware accelerators for physical layer Baseband Processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software-programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and Network-on-chip (NoC). We propose SPECTRUM, a predictable, software-defined many-core architecture that exploits the massive parallelism of the LTE/5G Baseband Processing workload. The focus is on designing scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms. SPECTRUM employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled NoC that orchestrates the communication to avoid any contention, and per-core software-controlled scratchpad memory with deterministic access latency. Compared to many-core architecture like Skylake-SP (average power 215 W) that drops 14% packets at high-traffic load, 256-core SPECTRUM by definition has zero packet drop rate at significantly lower average power of 24 W. SPECTRUM consumes 2.11× lower power than C66x DSP cores+accelerator platform in Baseband Processing. We also enable SPECTRUM to handle dynamic workloads with multiple service categories present in 5G mobile network (Enhanced Mobile Broadband (eMBB), Ultra-reliable and Low-latency Communications (URLLC), and Massive Machine Type Communications (mMTC)), using a run-time scheduling and mapping algorithm. Experimental evaluations show that our algorithm performs task/NoC mapping at run-time on fewer cores compared to the static mapping (that reserves cores exclusively for each service category) while still meeting the differentiated latency and reliability requirements.
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time predictable software defined architecture with sdf based compiler flow for 5g Baseband Processing
International Conference on Acoustics Speech and Signal Processing, 2020Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Bruno Bodin, Lishiuan PehAbstract:The advent of 5G networks motivates the need for high-performance, low-power, time-predictable hardware that can handle the aggressive real-time latency and throughput requirements of Baseband Processing. With newer generations like 5G, programmable hardware that can adapt readily to network specification updates becomes a critical requirement. We introduce a software-defined array-based many-core architecture, called SPECTRUM, that couples lightweight predictable hardware components with a compiler flow that orchestrates the on-chip hardware resources. This design, by construction, provides timing guarantees with a programmable architecture. Our architecture and compiler flow are designed to support basestation Baseband Processing computation represented using deterministic Synchronous Data Flow (SDF) model of computation. SDF is commonly used to represent signal Processing applications and fits well with real-time systems requirements. We demonstrate substantial power savings with SPECTRUM compared to existing DSPs while meeting the performance requirements.
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spectrum a software defined predictable many core architecture for lte Baseband Processing
Languages Compilers and Tools for Embedded Systems, 2019Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Lishiuan PehAbstract:Wireless communication standards such as Long Term Evolution (LTE) are rapidly changing to support the high data rate of wireless devices. The physical layer Baseband Processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing base station transceivers utilize customized Digital Signal Processing (DSP) cores or fixed-function hardware accelerators for physical layer Baseband Processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and network-on chip. We propose SPECTRUM, a predictable software defined many-core architecture that exploits the massive parallelism of the LTE Baseband Processing. The focus is on designing a scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms. SPECTRUM employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled on-chip network that orchestrates the communication to avoid any contention and per-core software controlled scratchpad memory with deterministic access latency. Compared to a many-core architecture like Skylake-SP (average power 215W) that drops 14% packets at high traffic load, 256-core SPECTRUM by definition has zero packet drop rate at significantly lower average power of 24W. SPECTRUM consumes 2.11x lower power than C66x DSP cores+accelerator platform in Baseband Processing. SPECTRUM is also well-positioned to support future 5G workloads.
Vanchinathan Venkataramani - One of the best experts on this subject based on the ideXlab platform.
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spectrum a software defined predictable many core architecture for lte 5g Baseband Processing
ACM Transactions in Embedded Computing Systems, 2020Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Lishiuan PehAbstract:Wireless communication standards such as Long-term Evolution (LTE) are rapidly changing to support the high data-rate of wireless devices. The physical layer Baseband Processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing basestation transceivers utilize customized DSP cores or fixed-function hardware accelerators for physical layer Baseband Processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software-programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and Network-on-chip (NoC). We propose SPECTRUM, a predictable, software-defined many-core architecture that exploits the massive parallelism of the LTE/5G Baseband Processing workload. The focus is on designing scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms. SPECTRUM employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled NoC that orchestrates the communication to avoid any contention, and per-core software-controlled scratchpad memory with deterministic access latency. Compared to many-core architecture like Skylake-SP (average power 215 W) that drops 14% packets at high-traffic load, 256-core SPECTRUM by definition has zero packet drop rate at significantly lower average power of 24 W. SPECTRUM consumes 2.11× lower power than C66x DSP cores+accelerator platform in Baseband Processing. We also enable SPECTRUM to handle dynamic workloads with multiple service categories present in 5G mobile network (Enhanced Mobile Broadband (eMBB), Ultra-reliable and Low-latency Communications (URLLC), and Massive Machine Type Communications (mMTC)), using a run-time scheduling and mapping algorithm. Experimental evaluations show that our algorithm performs task/NoC mapping at run-time on fewer cores compared to the static mapping (that reserves cores exclusively for each service category) while still meeting the differentiated latency and reliability requirements.
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time predictable software defined architecture with sdf based compiler flow for 5g Baseband Processing
International Conference on Acoustics Speech and Signal Processing, 2020Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Bruno Bodin, Lishiuan PehAbstract:The advent of 5G networks motivates the need for high-performance, low-power, time-predictable hardware that can handle the aggressive real-time latency and throughput requirements of Baseband Processing. With newer generations like 5G, programmable hardware that can adapt readily to network specification updates becomes a critical requirement. We introduce a software-defined array-based many-core architecture, called SPECTRUM, that couples lightweight predictable hardware components with a compiler flow that orchestrates the on-chip hardware resources. This design, by construction, provides timing guarantees with a programmable architecture. Our architecture and compiler flow are designed to support basestation Baseband Processing computation represented using deterministic Synchronous Data Flow (SDF) model of computation. SDF is commonly used to represent signal Processing applications and fits well with real-time systems requirements. We demonstrate substantial power savings with SPECTRUM compared to existing DSPs while meeting the performance requirements.
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spectrum a software defined predictable many core architecture for lte Baseband Processing
Languages Compilers and Tools for Embedded Systems, 2019Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Lishiuan PehAbstract:Wireless communication standards such as Long Term Evolution (LTE) are rapidly changing to support the high data rate of wireless devices. The physical layer Baseband Processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing base station transceivers utilize customized Digital Signal Processing (DSP) cores or fixed-function hardware accelerators for physical layer Baseband Processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and network-on chip. We propose SPECTRUM, a predictable software defined many-core architecture that exploits the massive parallelism of the LTE Baseband Processing. The focus is on designing a scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms. SPECTRUM employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled on-chip network that orchestrates the communication to avoid any contention and per-core software controlled scratchpad memory with deterministic access latency. Compared to a many-core architecture like Skylake-SP (average power 215W) that drops 14% packets at high traffic load, 256-core SPECTRUM by definition has zero packet drop rate at significantly lower average power of 24W. SPECTRUM consumes 2.11x lower power than C66x DSP cores+accelerator platform in Baseband Processing. SPECTRUM is also well-positioned to support future 5G workloads.
Tulika Mitra - One of the best experts on this subject based on the ideXlab platform.
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spectrum a software defined predictable many core architecture for lte 5g Baseband Processing
ACM Transactions in Embedded Computing Systems, 2020Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Lishiuan PehAbstract:Wireless communication standards such as Long-term Evolution (LTE) are rapidly changing to support the high data-rate of wireless devices. The physical layer Baseband Processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing basestation transceivers utilize customized DSP cores or fixed-function hardware accelerators for physical layer Baseband Processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software-programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and Network-on-chip (NoC). We propose SPECTRUM, a predictable, software-defined many-core architecture that exploits the massive parallelism of the LTE/5G Baseband Processing workload. The focus is on designing scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms. SPECTRUM employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled NoC that orchestrates the communication to avoid any contention, and per-core software-controlled scratchpad memory with deterministic access latency. Compared to many-core architecture like Skylake-SP (average power 215 W) that drops 14% packets at high-traffic load, 256-core SPECTRUM by definition has zero packet drop rate at significantly lower average power of 24 W. SPECTRUM consumes 2.11× lower power than C66x DSP cores+accelerator platform in Baseband Processing. We also enable SPECTRUM to handle dynamic workloads with multiple service categories present in 5G mobile network (Enhanced Mobile Broadband (eMBB), Ultra-reliable and Low-latency Communications (URLLC), and Massive Machine Type Communications (mMTC)), using a run-time scheduling and mapping algorithm. Experimental evaluations show that our algorithm performs task/NoC mapping at run-time on fewer cores compared to the static mapping (that reserves cores exclusively for each service category) while still meeting the differentiated latency and reliability requirements.
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time predictable software defined architecture with sdf based compiler flow for 5g Baseband Processing
International Conference on Acoustics Speech and Signal Processing, 2020Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Bruno Bodin, Lishiuan PehAbstract:The advent of 5G networks motivates the need for high-performance, low-power, time-predictable hardware that can handle the aggressive real-time latency and throughput requirements of Baseband Processing. With newer generations like 5G, programmable hardware that can adapt readily to network specification updates becomes a critical requirement. We introduce a software-defined array-based many-core architecture, called SPECTRUM, that couples lightweight predictable hardware components with a compiler flow that orchestrates the on-chip hardware resources. This design, by construction, provides timing guarantees with a programmable architecture. Our architecture and compiler flow are designed to support basestation Baseband Processing computation represented using deterministic Synchronous Data Flow (SDF) model of computation. SDF is commonly used to represent signal Processing applications and fits well with real-time systems requirements. We demonstrate substantial power savings with SPECTRUM compared to existing DSPs while meeting the performance requirements.
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spectrum a software defined predictable many core architecture for lte Baseband Processing
Languages Compilers and Tools for Embedded Systems, 2019Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Lishiuan PehAbstract:Wireless communication standards such as Long Term Evolution (LTE) are rapidly changing to support the high data rate of wireless devices. The physical layer Baseband Processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing base station transceivers utilize customized Digital Signal Processing (DSP) cores or fixed-function hardware accelerators for physical layer Baseband Processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and network-on chip. We propose SPECTRUM, a predictable software defined many-core architecture that exploits the massive parallelism of the LTE Baseband Processing. The focus is on designing a scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms. SPECTRUM employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled on-chip network that orchestrates the communication to avoid any contention and per-core software controlled scratchpad memory with deterministic access latency. Compared to a many-core architecture like Skylake-SP (average power 215W) that drops 14% packets at high traffic load, 256-core SPECTRUM by definition has zero packet drop rate at significantly lower average power of 24W. SPECTRUM consumes 2.11x lower power than C66x DSP cores+accelerator platform in Baseband Processing. SPECTRUM is also well-positioned to support future 5G workloads.
Aditi Kulkarni - One of the best experts on this subject based on the ideXlab platform.
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spectrum a software defined predictable many core architecture for lte 5g Baseband Processing
ACM Transactions in Embedded Computing Systems, 2020Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Lishiuan PehAbstract:Wireless communication standards such as Long-term Evolution (LTE) are rapidly changing to support the high data-rate of wireless devices. The physical layer Baseband Processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing basestation transceivers utilize customized DSP cores or fixed-function hardware accelerators for physical layer Baseband Processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software-programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and Network-on-chip (NoC). We propose SPECTRUM, a predictable, software-defined many-core architecture that exploits the massive parallelism of the LTE/5G Baseband Processing workload. The focus is on designing scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms. SPECTRUM employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled NoC that orchestrates the communication to avoid any contention, and per-core software-controlled scratchpad memory with deterministic access latency. Compared to many-core architecture like Skylake-SP (average power 215 W) that drops 14% packets at high-traffic load, 256-core SPECTRUM by definition has zero packet drop rate at significantly lower average power of 24 W. SPECTRUM consumes 2.11× lower power than C66x DSP cores+accelerator platform in Baseband Processing. We also enable SPECTRUM to handle dynamic workloads with multiple service categories present in 5G mobile network (Enhanced Mobile Broadband (eMBB), Ultra-reliable and Low-latency Communications (URLLC), and Massive Machine Type Communications (mMTC)), using a run-time scheduling and mapping algorithm. Experimental evaluations show that our algorithm performs task/NoC mapping at run-time on fewer cores compared to the static mapping (that reserves cores exclusively for each service category) while still meeting the differentiated latency and reliability requirements.
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time predictable software defined architecture with sdf based compiler flow for 5g Baseband Processing
International Conference on Acoustics Speech and Signal Processing, 2020Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Bruno Bodin, Lishiuan PehAbstract:The advent of 5G networks motivates the need for high-performance, low-power, time-predictable hardware that can handle the aggressive real-time latency and throughput requirements of Baseband Processing. With newer generations like 5G, programmable hardware that can adapt readily to network specification updates becomes a critical requirement. We introduce a software-defined array-based many-core architecture, called SPECTRUM, that couples lightweight predictable hardware components with a compiler flow that orchestrates the on-chip hardware resources. This design, by construction, provides timing guarantees with a programmable architecture. Our architecture and compiler flow are designed to support basestation Baseband Processing computation represented using deterministic Synchronous Data Flow (SDF) model of computation. SDF is commonly used to represent signal Processing applications and fits well with real-time systems requirements. We demonstrate substantial power savings with SPECTRUM compared to existing DSPs while meeting the performance requirements.
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spectrum a software defined predictable many core architecture for lte Baseband Processing
Languages Compilers and Tools for Embedded Systems, 2019Co-Authors: Vanchinathan Venkataramani, Aditi Kulkarni, Tulika Mitra, Lishiuan PehAbstract:Wireless communication standards such as Long Term Evolution (LTE) are rapidly changing to support the high data rate of wireless devices. The physical layer Baseband Processing has strict real-time deadlines, especially in the next-generation applications enabled by the 5G standard. Existing base station transceivers utilize customized Digital Signal Processing (DSP) cores or fixed-function hardware accelerators for physical layer Baseband Processing. However, these approaches incur significant non-recurring engineering costs and are inflexible to newer standards or updates. Software programmable processors offer more adaptability. However, it is challenging to sustain guaranteed worst-case latency and throughput at reasonably low-power on shared-memory many-core architectures featuring inherently unpredictable design choices, such as caches and network-on chip. We propose SPECTRUM, a predictable software defined many-core architecture that exploits the massive parallelism of the LTE Baseband Processing. The focus is on designing a scalable lightweight hardware that can be programmed and defined by sophisticated software mechanisms. SPECTRUM employs hundreds of lightweight in-order cores augmented with custom instructions that provide predictable timing, a purely software-scheduled on-chip network that orchestrates the communication to avoid any contention and per-core software controlled scratchpad memory with deterministic access latency. Compared to a many-core architecture like Skylake-SP (average power 215W) that drops 14% packets at high traffic load, 256-core SPECTRUM by definition has zero packet drop rate at significantly lower average power of 24W. SPECTRUM consumes 2.11x lower power than C66x DSP cores+accelerator platform in Baseband Processing. SPECTRUM is also well-positioned to support future 5G workloads.
Shi Jin - One of the best experts on this subject based on the ideXlab platform.
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Spectral and Energy Efficiency of Massive MIMO for Hybrid Architectures Based on Phase Shifters
IEEE Access, 2018Co-Authors: Weiqiang Tan, Dongqing Xie, Junjuan Xia, Weijie Tan, Lisheng Fan, Shi JinAbstract:This paper investigates the downlink achievable spectral efficiency (SE) and energy efficiency (EE) of massive MIMO for hybrid architectures based on phase shifters, where the base station (BS) has perfect channel state information and Baseband Processing is done zero-forcing precoding. We derive an approximated upper bound on the achievable SE for hybrid architecture with ideal phase shifters. Based on the derived analytical expression, we find that the total achievable SE increases with the number of BS antennas and users and the signal-to-noise ratio (SNR). In order to acquire the required limited feedback, we propose an algorithm to generate the corresponding quantized matrix and study hybrid architectures with quantized phase shifters. Compared to full-digital architectures, results show that hybrid architectures enjoy a much higher achievable EE in massive MIMO systems, whereas its achievable SE is inferior to full-digital architectures. In addition, results also showcase that the achievable SE of hybrid architectures can be improved by increasing the bits of phase shifters, and there exists an optimal SNR and antenna number to maximize the achievable EE of the system.
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Spectral Efficiency of DFT-Based Processing Hybrid Architectures in Massive MIMO
IEEE Wireless Communications Letters, 2017Co-Authors: Weiqiang Tan, Michail Matthaiou, Shi JinAbstract:This letter investigates the achievable spectral efficiency (SE) of massive multiple-input multiple-output transmission systems with hybrid architectures based on discrete Fourier transform (DFT) Processing, where the base station (BS) has perfect channel state information and Baseband Processing is performed by zero-forcing precoding. We derive tractable upper and lower bounds on the achievable SE. Based on these results, the effects of the number of radio frequency (RF) chains, signal-to-noise ratio (SNR), and the number of users are revealed. Compared to hybrid architectures with ideal and quantized phase shifters, simulations indicate that the achievable SE with DFT Processing is inferior to the one with ideal phase shifters. In addition, the achievable SE with DFT Processing is independent of the number of BS antennas and can be improved by increasing the SNR and the number of RF chains, while there exists an optimal number of users that maximizes the total achievable SE.