The Experts below are selected from a list of 4113 Experts worldwide ranked by ideXlab platform
Pavan Kumar Hanumolu - One of the best experts on this subject based on the ideXlab platform.
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a 12 gb s 10 ns turn on time rapid on off Baud Rate dfe receiver in 65 nm cmos
IEEE Journal of Solid-state Circuits, 2020Co-Authors: Dong-wook Kim, Woo-seok Choi, Ahmed Elkholy, Mostafa G. Ahmed, Pavan Kumar HanumoluAbstract:Rapid ON/OFF (ROO) operation helps scale power in accordance with link utilization. In this article, we present a Baud-Rate ROO receiver that can turn on in just 10 ns (~120 UI). Baud-Rate clock and data recovery (CDR) is implemented using a new timing function that is amenable to operation with a loop un-rolled decision feedback equalizer (DFE). The receiver is turned on rapidly by sweeping the recovered clock phase across the received data bit by offsetting the digitally controlled oscillator (DCO) frequency at each power-ON event. This first ROO DFE receiver also includes a continuous-time linear equalizer (CTLE) and three-tap DFE to compensate up to 20-dB channel loss at Nyquist. Fabricated in a 65-nm CMOS process, the prototype receiver recovers 12 Gb/s with BER 30-MHz JTOL corner, 377 $fs_{\text {rms}}$ recovered clock jitter, and 3.8-pJ/bit energy efficiency.
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A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS
IEEE Journal of Solid-State Circuits, 2020Co-Authors: Dong-wook Kim, Woo-seok Choi, Ahmed Elkholy, Mostafa G. Ahmed, Pavan Kumar HanumoluAbstract:Rapid ON/OFF (ROO) operation helps scale power in accordance with link utilization. In this article, we present a Baud-Rate ROO receiver that can turn on in just 10 ns (~120 UI). Baud-Rate clock and data recovery (CDR) is implemented using a new timing function that is amenable to operation with a loop un-rolled decision feedback equalizer (DFE). The receiver is turned on rapidly by sweeping the recovered clock phase across the received data bit by offsetting the digitally controlled oscillator (DCO) frequency at each power-ON event. This first ROO DFE receiver also includes a continuous-time linear equalizer (CTLE) and three-tap DFE to compensate up to 20-dB channel loss at Nyquist. Fabricated in a 65-nm CMOS process, the prototype receiver recovers 12 Gb/s with BER 30-MHz JTOL corner, 377 $fs_{\text {rms}}$ recovered clock jitter, and 3.8-pJ/bit energy efficiency.
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A 15-Gb/s Sub-Baud-Rate Digital CDR
IEEE Journal of Solid-State Circuits, 2019Co-Authors: Dong-wook Kim, Woo-seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar HanumoluAbstract:This paper presents a sub-Baud-Rate clock and data recovery (CDR) circuit that can recover clock and data using only differential quarter-Rate clocks. A combination of eight samplers and an integrator recover four data bits in each clock cycle. Four of the eight samplers are re-used for phase detection as well as for background calibration to improve the robustness of the CDR to process, voltage, and temperature variations. A continuous-time linear equalizer is used to compensate for inter-symbol interference up to 11 dB. The CDR prototype fabricated in a 65-nm CMOS recovers 15.2-Gb/s data using only differential 3.8-GHz clock and achieves bit error Rate (BER) 10-MHz jitter tolerance (JTOL) corner, and 548 fsrms recovered clock jitter. The total power consumption is 29 mW, which translates to an energy efficiency of 1.9 pJ/bit.
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a 15gb s 1 9pj bit sub Baud Rate digital cdr
Custom Integrated Circuits Conference, 2018Co-Authors: Dong-wook Kim, Woo-seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar HanumoluAbstract:A sub-Baud-Rate CDR that can recover clock and data using only a quarter-Rate clock is presented. Four data bits are recovered in each clock cycle using eight samplers and a current integrator. Four of the eight samplers used for data recovery are re-used for phase detection. Fabricated in a 65nm CMOS process and operating with 11dB channel loss, the prototype CDR recovers 15.2Gb/s data using a 3.8GHz clock and achieves BER 10MHz JTOL corner, 548fs rms recovered clock jitter, and 1.9pJ/bit energy efficiency.
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CICC - A 15Gb/s 1.9pJ/bit sub-Baud-Rate digital CDR
2018 IEEE Custom Integrated Circuits Conference (CICC), 2018Co-Authors: Dong-wook Kim, Woo-seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar HanumoluAbstract:A sub-Baud-Rate CDR that can recover clock and data using only a quarter-Rate clock is presented. Four data bits are recovered in each clock cycle using eight samplers and a current integrator. Four of the eight samplers used for data recovery are re-used for phase detection. Fabricated in a 65nm CMOS process and operating with 11dB channel loss, the prototype CDR recovers 15.2Gb/s data using a 3.8GHz clock and achieves BER 10MHz JTOL corner, 548fs rms recovered clock jitter, and 1.9pJ/bit energy efficiency.
Dong-wook Kim - One of the best experts on this subject based on the ideXlab platform.
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a 12 gb s 10 ns turn on time rapid on off Baud Rate dfe receiver in 65 nm cmos
IEEE Journal of Solid-state Circuits, 2020Co-Authors: Dong-wook Kim, Woo-seok Choi, Ahmed Elkholy, Mostafa G. Ahmed, Pavan Kumar HanumoluAbstract:Rapid ON/OFF (ROO) operation helps scale power in accordance with link utilization. In this article, we present a Baud-Rate ROO receiver that can turn on in just 10 ns (~120 UI). Baud-Rate clock and data recovery (CDR) is implemented using a new timing function that is amenable to operation with a loop un-rolled decision feedback equalizer (DFE). The receiver is turned on rapidly by sweeping the recovered clock phase across the received data bit by offsetting the digitally controlled oscillator (DCO) frequency at each power-ON event. This first ROO DFE receiver also includes a continuous-time linear equalizer (CTLE) and three-tap DFE to compensate up to 20-dB channel loss at Nyquist. Fabricated in a 65-nm CMOS process, the prototype receiver recovers 12 Gb/s with BER 30-MHz JTOL corner, 377 $fs_{\text {rms}}$ recovered clock jitter, and 3.8-pJ/bit energy efficiency.
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A 12-Gb/s 10-ns Turn-On Time Rapid ON/OFF Baud-Rate DFE Receiver in 65-nm CMOS
IEEE Journal of Solid-State Circuits, 2020Co-Authors: Dong-wook Kim, Woo-seok Choi, Ahmed Elkholy, Mostafa G. Ahmed, Pavan Kumar HanumoluAbstract:Rapid ON/OFF (ROO) operation helps scale power in accordance with link utilization. In this article, we present a Baud-Rate ROO receiver that can turn on in just 10 ns (~120 UI). Baud-Rate clock and data recovery (CDR) is implemented using a new timing function that is amenable to operation with a loop un-rolled decision feedback equalizer (DFE). The receiver is turned on rapidly by sweeping the recovered clock phase across the received data bit by offsetting the digitally controlled oscillator (DCO) frequency at each power-ON event. This first ROO DFE receiver also includes a continuous-time linear equalizer (CTLE) and three-tap DFE to compensate up to 20-dB channel loss at Nyquist. Fabricated in a 65-nm CMOS process, the prototype receiver recovers 12 Gb/s with BER 30-MHz JTOL corner, 377 $fs_{\text {rms}}$ recovered clock jitter, and 3.8-pJ/bit energy efficiency.
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A 15-Gb/s Sub-Baud-Rate Digital CDR
IEEE Journal of Solid-State Circuits, 2019Co-Authors: Dong-wook Kim, Woo-seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar HanumoluAbstract:This paper presents a sub-Baud-Rate clock and data recovery (CDR) circuit that can recover clock and data using only differential quarter-Rate clocks. A combination of eight samplers and an integrator recover four data bits in each clock cycle. Four of the eight samplers are re-used for phase detection as well as for background calibration to improve the robustness of the CDR to process, voltage, and temperature variations. A continuous-time linear equalizer is used to compensate for inter-symbol interference up to 11 dB. The CDR prototype fabricated in a 65-nm CMOS recovers 15.2-Gb/s data using only differential 3.8-GHz clock and achieves bit error Rate (BER) 10-MHz jitter tolerance (JTOL) corner, and 548 fsrms recovered clock jitter. The total power consumption is 29 mW, which translates to an energy efficiency of 1.9 pJ/bit.
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a 15gb s 1 9pj bit sub Baud Rate digital cdr
Custom Integrated Circuits Conference, 2018Co-Authors: Dong-wook Kim, Woo-seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar HanumoluAbstract:A sub-Baud-Rate CDR that can recover clock and data using only a quarter-Rate clock is presented. Four data bits are recovered in each clock cycle using eight samplers and a current integrator. Four of the eight samplers used for data recovery are re-used for phase detection. Fabricated in a 65nm CMOS process and operating with 11dB channel loss, the prototype CDR recovers 15.2Gb/s data using a 3.8GHz clock and achieves BER 10MHz JTOL corner, 548fs rms recovered clock jitter, and 1.9pJ/bit energy efficiency.
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CICC - A 15Gb/s 1.9pJ/bit sub-Baud-Rate digital CDR
2018 IEEE Custom Integrated Circuits Conference (CICC), 2018Co-Authors: Dong-wook Kim, Woo-seok Choi, Ahmed Elkholy, Jack Kenney, Pavan Kumar HanumoluAbstract:A sub-Baud-Rate CDR that can recover clock and data using only a quarter-Rate clock is presented. Four data bits are recovered in each clock cycle using eight samplers and a current integrator. Four of the eight samplers used for data recovery are re-used for phase detection. Fabricated in a 65nm CMOS process and operating with 11dB channel loss, the prototype CDR recovers 15.2Gb/s data using a 3.8GHz clock and achieves BER 10MHz JTOL corner, 548fs rms recovered clock jitter, and 1.9pJ/bit energy efficiency.
Hao Ming - One of the best experts on this subject based on the ideXlab platform.
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Inter-channel fiber nonlinearity mitigation in high Baud-Rate optical communication systems
Journal of Lightwave Technology, 2020Co-Authors: Fan Zhang, Lei Zhang, Xiaoke Ruan, Fan Yang, Hao Ming, Xinyu Chen, Zhangyuan Chen, Chuanchuan YangAbstract:Kerr nonlinearity in long distance fiber-optic link imposes a fundamental limitation to the capacity of wavelength division multiplexed (WDM) optical communication systems. Solving the inverse-propagating nonlinear Schrodinger equation (NLSE) is in principle a fundamental methodology to mitigate fiber nonlinear impairments. However, solving multi-channel coupled NLSE is too complexed to be implemented commercially. It is of great importance to compensate for nonlinear distortions in high Baud-Rate WDM systems based on the information of one single target channel. In this paper, we experimentally study fiber nonlinearity mitigation in an 8×512Gb/s (64GBaud) polarization division multiplexed (PDM) 16-ary quadrature amplitude modulation (16-QAM) Nyquist-WDM system with 960km standard single mode fiber (SSMF) loop transmission. The digital back-propagation (DBP) algorithm based on the target channel is applied, which can compensate for intra-channel nonlinearity. The inter-channel nonlinearity of cross phase modulation (XPM) induces nonlinear polarization scattering and nonlinear phase noise, which are partially correlated over adjacent pulses in high Baud-Rate systems. We propose an advanced nonlinear polarization crosstalk canceller (NPCC) with a novel decision feedback (DF) update stRategy that is called the DF-NPCC, which incorpoRates the iterative process of the least mean square (LMS) algorithm and can thus mitigate the correlated nonlinear polarization crosstalk and nonlinear phase noise. Through nonlinearity mitigation, the DBP together with the DF-NPCC can achieve a 0.77 dB Q 2 factor promotion. The DF-NPCC can suppress the remaining nonlinear distortions after the single channel DBP, which corresponds to a 0.36 dB Q 2 factor improvement due to inter-channel nonlinear mitigation. Our work indicates XPM distortions can be mitigated with low complexity digital signal processing such as the DF-NPCC based on the single channel information, which provides an attractive solution to compensate inter-channel fiber nonlinearity in high Baud-Rate Nyquist-WDM systems.
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High-Baud Rate Silicon Photonics for Short-reach Transmission
Asia Communications and Photonics Conference International Conference on Information Photonics and Optical Communications 2020 (ACP IPOC), 2020Co-Authors: Fan Zhang, Lei Zhang, Xiaoke Ruan, Fan Yang, Hao MingAbstract:We review high Baud Rate operation of Silicon photonic modulators and receivers with emphasize on short-reach applications. The current status of both devices and digital signal processing are discussed. © 2020 The Author(s)
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High Baud Rate Transmission With Silicon Photonic Modulators
IEEE Journal of Selected Topics in Quantum Electronics, 1Co-Authors: Fan Zhang, Lei Zhang, Xiaoke Ruan, Fan Yang, Hao MingAbstract:We review high Baud Rate operation of silicon photonic modulators with emphasis on short-reach and metro-haul applications. The current status of both devices and digital signal processing are discussed. The basic design of a typical carrier-depletion-based dual-drive traveling-wave Mach-Zehnder modulator (TW-MZM) is studied by simulation. Based on an all-silicon TW-MZM, we report the transmission experiments of high Baud Rate single sideband 4-ary pulse amplitude modulation (PAM-4) signals with linear equalization and artificial neural network based equalization, respectively. Our work indicates all-silicon modulators can address the requirements of future optical communication systems operating at 100 GBaud.
Mark Horowitz - One of the best experts on this subject based on the ideXlab platform.
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CMOS transceiver with Baud Rate clock recovery for optical interconnects
2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), 1Co-Authors: Azita Emami-neyestanak, Samuel Palermo, Hae-chang Lee, Mark HorowitzAbstract:An efficient Baud Rate clock and data recovery architecture is applied to a double sampling/integrating front-end receiver for optical interconnects. Receiver performance is analyzed and projected for future technologies. This front-end allows use of a 1:5 demux architecture to achieve 5Gb/s in a 0.25 /spl mu/m CMOS process. A 5:1 multiplexing transmitter is used to drive VCSELs for optical transmission. The transceiver chip consumes 145mW per link at 5Gb/s with a 2.5V supply.
Fan Zhang - One of the best experts on this subject based on the ideXlab platform.
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Inter-channel fiber nonlinearity mitigation in high Baud-Rate optical communication systems
Journal of Lightwave Technology, 2020Co-Authors: Fan Zhang, Lei Zhang, Xiaoke Ruan, Fan Yang, Hao Ming, Xinyu Chen, Zhangyuan Chen, Chuanchuan YangAbstract:Kerr nonlinearity in long distance fiber-optic link imposes a fundamental limitation to the capacity of wavelength division multiplexed (WDM) optical communication systems. Solving the inverse-propagating nonlinear Schrodinger equation (NLSE) is in principle a fundamental methodology to mitigate fiber nonlinear impairments. However, solving multi-channel coupled NLSE is too complexed to be implemented commercially. It is of great importance to compensate for nonlinear distortions in high Baud-Rate WDM systems based on the information of one single target channel. In this paper, we experimentally study fiber nonlinearity mitigation in an 8×512Gb/s (64GBaud) polarization division multiplexed (PDM) 16-ary quadrature amplitude modulation (16-QAM) Nyquist-WDM system with 960km standard single mode fiber (SSMF) loop transmission. The digital back-propagation (DBP) algorithm based on the target channel is applied, which can compensate for intra-channel nonlinearity. The inter-channel nonlinearity of cross phase modulation (XPM) induces nonlinear polarization scattering and nonlinear phase noise, which are partially correlated over adjacent pulses in high Baud-Rate systems. We propose an advanced nonlinear polarization crosstalk canceller (NPCC) with a novel decision feedback (DF) update stRategy that is called the DF-NPCC, which incorpoRates the iterative process of the least mean square (LMS) algorithm and can thus mitigate the correlated nonlinear polarization crosstalk and nonlinear phase noise. Through nonlinearity mitigation, the DBP together with the DF-NPCC can achieve a 0.77 dB Q 2 factor promotion. The DF-NPCC can suppress the remaining nonlinear distortions after the single channel DBP, which corresponds to a 0.36 dB Q 2 factor improvement due to inter-channel nonlinear mitigation. Our work indicates XPM distortions can be mitigated with low complexity digital signal processing such as the DF-NPCC based on the single channel information, which provides an attractive solution to compensate inter-channel fiber nonlinearity in high Baud-Rate Nyquist-WDM systems.
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High-Baud Rate Silicon Photonics for Short-reach Transmission
Asia Communications and Photonics Conference International Conference on Information Photonics and Optical Communications 2020 (ACP IPOC), 2020Co-Authors: Fan Zhang, Lei Zhang, Xiaoke Ruan, Fan Yang, Hao MingAbstract:We review high Baud Rate operation of Silicon photonic modulators and receivers with emphasize on short-reach applications. The current status of both devices and digital signal processing are discussed. © 2020 The Author(s)
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High Baud Rate Transmission With Silicon Photonic Modulators
IEEE Journal of Selected Topics in Quantum Electronics, 1Co-Authors: Fan Zhang, Lei Zhang, Xiaoke Ruan, Fan Yang, Hao MingAbstract:We review high Baud Rate operation of silicon photonic modulators with emphasis on short-reach and metro-haul applications. The current status of both devices and digital signal processing are discussed. The basic design of a typical carrier-depletion-based dual-drive traveling-wave Mach-Zehnder modulator (TW-MZM) is studied by simulation. Based on an all-silicon TW-MZM, we report the transmission experiments of high Baud Rate single sideband 4-ary pulse amplitude modulation (PAM-4) signals with linear equalization and artificial neural network based equalization, respectively. Our work indicates all-silicon modulators can address the requirements of future optical communication systems operating at 100 GBaud.
