The Experts below are selected from a list of 7116 Experts worldwide ranked by ideXlab platform

Radovan Stojanovic - One of the best experts on this subject based on the ideXlab platform.

  • single clock square root algorithm based on Binomial Series and its fpga implementation
    Mediterranean Conference on Embedded Computing, 2018
    Co-Authors: Tomas Bagala, Adam Fibich, Miroslav Hagara, Peter Kubinec, Oldrich Ondracek, Vladimir Stofanik, Radovan Stojanovic
    Abstract:

    Signal processing is frequently discussed topic nowadays. Digital Signal Processors (DSP) or Field Programmable Gate Array (FPGA) can process data at high rates. Arithmetic operations such as addition, subtraction, multiplication, division or square root are often used in DSP and FPGA. Several algorithms for square root computation on FPGA were designed in past years. This paper describes a proposal of single clock square root algorithm applicable on FPGA. The algorithm is formulated generally for any number of bits. Simulations and experiments for 16-bits binary numbers have confirmed that obtained results are equal to square root values rounded to nearest integer.

  • MECO - Single clock square root algorithm based on Binomial Series and its FPGA implementation
    2018 7th Mediterranean Conference on Embedded Computing (MECO), 2018
    Co-Authors: Tomas Bagala, Adam Fibich, Miroslav Hagara, Peter Kubinec, Oldrich Ondracek, Vladimir Stofanik, Radovan Stojanovic
    Abstract:

    Signal processing is frequently discussed topic nowadays. Digital Signal Processors (DSP) or Field Programmable Gate Array (FPGA) can process data at high rates. Arithmetic operations such as addition, subtraction, multiplication, division or square root are often used in DSP and FPGA. Several algorithms for square root computation on FPGA were designed in past years. This paper describes a proposal of single clock square root algorithm applicable on FPGA. The algorithm is formulated generally for any number of bits. Simulations and experiments for 16-bits binary numbers have confirmed that obtained results are equal to square root values rounded to nearest integer.

P O Babatola - One of the best experts on this subject based on the ideXlab platform.

Mark W. Coffey - One of the best experts on this subject based on the ideXlab platform.

  • Series of zeta values, the Stieltjes constants, and a
    2009
    Co-Authors: Mark W. Coffey
    Abstract:

    We present a variety of Series representations of the Stieltjes and related constants, the Stieltjes constants being the coefficients ofthe Laurent expansion of the Hurwitz zeta function �(s,a) about s = 1. Additionally we obtain Series and integral representations of a sum Sγ(n) formed as an alternating Binomial Series from the Stieltjes constants. The slowly varying sum Sγ(n) + n is an important subsum in application of the Li criterion for the Riemann hypothesis.

  • On harmonic Binomial Series
    arXiv: Mathematical Physics, 2008
    Co-Authors: Mark W. Coffey
    Abstract:

    We evaluate Binomial Series with harmonic number coefficients, providing recursion relations, integral representations, and several examples. The results are of interest to analytic number theory, the analysis of algorithms, and calculations of theoretical physics, as well as other applications.

  • Series of zeta values, the Stieltjes constants, and a sum S_\gamma(n)
    arXiv: Mathematical Physics, 2007
    Co-Authors: Mark W. Coffey
    Abstract:

    We present a variety of Series representations of the Stieltjes and related constants, the Stieltjes constants being the coefficients of the Laurent expansion of the Hurwitz zeta function zeta(s,a) about s=1. Additionally we obtain Series and integral representations of a sum S_\gamma(n) formed as an alternating Binomial Series from the Stieltjes constants. The slowly varying sum S_\gamma(n)+n is an important subsum in application of the Li criterion for the Riemann hypothesis.

Joseph D. Warfield - One of the best experts on this subject based on the ideXlab platform.

  • Objective Comparison of Confidence Bound Methods for Binomial Series System Reliability
    IEEE Transactions on Reliability, 2020
    Co-Authors: Edward Schuberg, Janet Myhre, Daniel R. Jeske, Allan D. Mcquarrie, Joseph D. Warfield
    Abstract:

    Obtaining lower confidence bounds on the reliability of a Series system remains a problem of interest. Engineers and practitioners desire methods with good properties to obtain lower confidence bounds when only component-level Binomial test data are available. With numerous methods proposed in the literature–none of which are uniformly superior–it can be an overwhelming task to select the method which best handles the scenario at hand. We develop a software tool in R (available in the “Serieslcb” package) through which users can discover the methods that best suit their situation. The tool runs user-defined simulations and then ranks the best performing methods based on objective comparisons utilizing a delta coverage metric. This article outlines the methods and comparison strategy implemented in the package. It also discusses the design of the software tool and illustrates it with an example.

Tomas Bagala - One of the best experts on this subject based on the ideXlab platform.

  • single clock square root algorithm based on Binomial Series and its fpga implementation
    Mediterranean Conference on Embedded Computing, 2018
    Co-Authors: Tomas Bagala, Adam Fibich, Miroslav Hagara, Peter Kubinec, Oldrich Ondracek, Vladimir Stofanik, Radovan Stojanovic
    Abstract:

    Signal processing is frequently discussed topic nowadays. Digital Signal Processors (DSP) or Field Programmable Gate Array (FPGA) can process data at high rates. Arithmetic operations such as addition, subtraction, multiplication, division or square root are often used in DSP and FPGA. Several algorithms for square root computation on FPGA were designed in past years. This paper describes a proposal of single clock square root algorithm applicable on FPGA. The algorithm is formulated generally for any number of bits. Simulations and experiments for 16-bits binary numbers have confirmed that obtained results are equal to square root values rounded to nearest integer.

  • MECO - Single clock square root algorithm based on Binomial Series and its FPGA implementation
    2018 7th Mediterranean Conference on Embedded Computing (MECO), 2018
    Co-Authors: Tomas Bagala, Adam Fibich, Miroslav Hagara, Peter Kubinec, Oldrich Ondracek, Vladimir Stofanik, Radovan Stojanovic
    Abstract:

    Signal processing is frequently discussed topic nowadays. Digital Signal Processors (DSP) or Field Programmable Gate Array (FPGA) can process data at high rates. Arithmetic operations such as addition, subtraction, multiplication, division or square root are often used in DSP and FPGA. Several algorithms for square root computation on FPGA were designed in past years. This paper describes a proposal of single clock square root algorithm applicable on FPGA. The algorithm is formulated generally for any number of bits. Simulations and experiments for 16-bits binary numbers have confirmed that obtained results are equal to square root values rounded to nearest integer.