The Experts below are selected from a list of 1326 Experts worldwide ranked by ideXlab platform
Sukhdev Roy - One of the best experts on this subject based on the ideXlab platform.
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all optical ultrafast xor xnor logic gates binary Counter and double Bit comparator with silicon microring resonators
Applied Optics, 2014Co-Authors: Purnima Sethi, Sukhdev RoyAbstract:We present designs of all-optical ultrafast YES/NOT, XOR/XNOR logic gates, binary Counter, and double-Bit comparator based on all-optical switching by two-photon absorption induced free-carrier injection in silicon 2×2 add–drop microring resonators. The proposed circuits have been theoretically analyzed using time-domain coupled-mode theory based on reported experimental values to realize low power (∼28 mW) ultrafast (∼22 ps) operation with high modulation (80%) and Bit rate (45 Gb/s). The designs are complementary metal-oxide semiconductor compatible and provide advantages of high Q-factor, tunability, compactness, cascadibility, scalability, reconfigurability, simplicity, and minimal number of switches and inputs for realization of the desired logic. Although a two-Bit Counter has been shown, the scheme can easily be extended to N-Bit Counter through cascading.
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All-optical ultrafast XOR/XNOR logic gates, binary Counter, and double-Bit comparator with silicon microring resonators.
Applied Optics, 2014Co-Authors: Purnima Sethi, Sukhdev RoyAbstract:We present designs of all-optical ultrafast YES/NOT, XOR/XNOR logic gates, binary Counter, and double-Bit comparator based on all-optical switching by two-photon absorption induced free-carrier injection in silicon 2×2 add–drop microring resonators. The proposed circuits have been theoretically analyzed using time-domain coupled-mode theory based on reported experimental values to realize low power (∼28 mW) ultrafast (∼22 ps) operation with high modulation (80%) and Bit rate (45 Gb/s). The designs are complementary metal-oxide semiconductor compatible and provide advantages of high Q-factor, tunability, compactness, cascadibility, scalability, reconfigurability, simplicity, and minimal number of switches and inputs for realization of the desired logic. Although a two-Bit Counter has been shown, the scheme can easily be extended to N-Bit Counter through cascading.
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Ultrafast All-Optical Flip-Flop and Binary Counter using Silicon Microring Resonators
12th International Conference on Fiber Optics and Photonics, 2014Co-Authors: Purnima Sethi, Sukhdev RoyAbstract:We present the design of a 45 Gb/s compact CMOS-compatible all-optical SR flip-flop and a 2-Bit Counter based on all-optical switching by two-photon absorption induced free-carrier injection in silicon 1 × 2 add-drop microring resonators.
Purnima Sethi - One of the best experts on this subject based on the ideXlab platform.
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all optical ultrafast xor xnor logic gates binary Counter and double Bit comparator with silicon microring resonators
Applied Optics, 2014Co-Authors: Purnima Sethi, Sukhdev RoyAbstract:We present designs of all-optical ultrafast YES/NOT, XOR/XNOR logic gates, binary Counter, and double-Bit comparator based on all-optical switching by two-photon absorption induced free-carrier injection in silicon 2×2 add–drop microring resonators. The proposed circuits have been theoretically analyzed using time-domain coupled-mode theory based on reported experimental values to realize low power (∼28 mW) ultrafast (∼22 ps) operation with high modulation (80%) and Bit rate (45 Gb/s). The designs are complementary metal-oxide semiconductor compatible and provide advantages of high Q-factor, tunability, compactness, cascadibility, scalability, reconfigurability, simplicity, and minimal number of switches and inputs for realization of the desired logic. Although a two-Bit Counter has been shown, the scheme can easily be extended to N-Bit Counter through cascading.
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All-optical ultrafast XOR/XNOR logic gates, binary Counter, and double-Bit comparator with silicon microring resonators.
Applied Optics, 2014Co-Authors: Purnima Sethi, Sukhdev RoyAbstract:We present designs of all-optical ultrafast YES/NOT, XOR/XNOR logic gates, binary Counter, and double-Bit comparator based on all-optical switching by two-photon absorption induced free-carrier injection in silicon 2×2 add–drop microring resonators. The proposed circuits have been theoretically analyzed using time-domain coupled-mode theory based on reported experimental values to realize low power (∼28 mW) ultrafast (∼22 ps) operation with high modulation (80%) and Bit rate (45 Gb/s). The designs are complementary metal-oxide semiconductor compatible and provide advantages of high Q-factor, tunability, compactness, cascadibility, scalability, reconfigurability, simplicity, and minimal number of switches and inputs for realization of the desired logic. Although a two-Bit Counter has been shown, the scheme can easily be extended to N-Bit Counter through cascading.
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Ultrafast All-Optical Flip-Flop and Binary Counter using Silicon Microring Resonators
12th International Conference on Fiber Optics and Photonics, 2014Co-Authors: Purnima Sethi, Sukhdev RoyAbstract:We present the design of a 45 Gb/s compact CMOS-compatible all-optical SR flip-flop and a 2-Bit Counter based on all-optical switching by two-photon absorption induced free-carrier injection in silicon 1 × 2 add-drop microring resonators.
Zhan Huang - One of the best experts on this subject based on the ideXlab platform.
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ICA3PP (2) - HDCat: Effectively Identifying Hot Data in Large-Scale I/O Streams with Enhanced Temporal Locality
Algorithms and Architectures for Parallel Processing, 2015Co-Authors: Jiahao Chen, Yuhui Deng, Zhan HuangAbstract:Hot data is very important for optimizing modern computer systems. For example, the identified hot data can be employed to extend the lifespan of flash memory. However, it is very challenging to effectively identify hot data with low memory consumption and low runtime overhead. This paper proposes a Hot Data Catcher HDCat which can effectively identify hot data in large-scale I/O streams by leveraging enhanced temporal locality. HDCat only maintains a hot data queue and a candidate hot data queue to record the data access pattern by tracking limited data set, thus effectively reducing the memory consumption. Furthermore, HDCat adopts a D-Bit Counter and a recency-Bit to leverage both the frequency and recency contained in the data stream. Additionally, HDCat can significantly reduce the conversion between hot data and cold data. Real traces are used to evaluate the proposed approach. Experimental results demonstrate that HDCat significantly outperforms the state-of-the-art Multi-hash algorithm and the two-level LRU algorithm.
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hdcat effectively identifying hot data in large scale i o streams with enhanced temporal locality
International Conference on Algorithms and Architectures for Parallel Processing, 2015Co-Authors: Jiahao Chen, Yuhui Deng, Zhan HuangAbstract:Hot data is very important for optimizing modern computer systems. For example, the identified hot data can be employed to extend the lifespan of flash memory. However, it is very challenging to effectively identify hot data with low memory consumption and low runtime overhead. This paper proposes a Hot Data Catcher HDCat which can effectively identify hot data in large-scale I/O streams by leveraging enhanced temporal locality. HDCat only maintains a hot data queue and a candidate hot data queue to record the data access pattern by tracking limited data set, thus effectively reducing the memory consumption. Furthermore, HDCat adopts a D-Bit Counter and a recency-Bit to leverage both the frequency and recency contained in the data stream. Additionally, HDCat can significantly reduce the conversion between hot data and cold data. Real traces are used to evaluate the proposed approach. Experimental results demonstrate that HDCat significantly outperforms the state-of-the-art Multi-hash algorithm and the two-level LRU algorithm.
Jiahao Chen - One of the best experts on this subject based on the ideXlab platform.
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ICA3PP (2) - HDCat: Effectively Identifying Hot Data in Large-Scale I/O Streams with Enhanced Temporal Locality
Algorithms and Architectures for Parallel Processing, 2015Co-Authors: Jiahao Chen, Yuhui Deng, Zhan HuangAbstract:Hot data is very important for optimizing modern computer systems. For example, the identified hot data can be employed to extend the lifespan of flash memory. However, it is very challenging to effectively identify hot data with low memory consumption and low runtime overhead. This paper proposes a Hot Data Catcher HDCat which can effectively identify hot data in large-scale I/O streams by leveraging enhanced temporal locality. HDCat only maintains a hot data queue and a candidate hot data queue to record the data access pattern by tracking limited data set, thus effectively reducing the memory consumption. Furthermore, HDCat adopts a D-Bit Counter and a recency-Bit to leverage both the frequency and recency contained in the data stream. Additionally, HDCat can significantly reduce the conversion between hot data and cold data. Real traces are used to evaluate the proposed approach. Experimental results demonstrate that HDCat significantly outperforms the state-of-the-art Multi-hash algorithm and the two-level LRU algorithm.
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hdcat effectively identifying hot data in large scale i o streams with enhanced temporal locality
International Conference on Algorithms and Architectures for Parallel Processing, 2015Co-Authors: Jiahao Chen, Yuhui Deng, Zhan HuangAbstract:Hot data is very important for optimizing modern computer systems. For example, the identified hot data can be employed to extend the lifespan of flash memory. However, it is very challenging to effectively identify hot data with low memory consumption and low runtime overhead. This paper proposes a Hot Data Catcher HDCat which can effectively identify hot data in large-scale I/O streams by leveraging enhanced temporal locality. HDCat only maintains a hot data queue and a candidate hot data queue to record the data access pattern by tracking limited data set, thus effectively reducing the memory consumption. Furthermore, HDCat adopts a D-Bit Counter and a recency-Bit to leverage both the frequency and recency contained in the data stream. Additionally, HDCat can significantly reduce the conversion between hot data and cold data. Real traces are used to evaluate the proposed approach. Experimental results demonstrate that HDCat significantly outperforms the state-of-the-art Multi-hash algorithm and the two-level LRU algorithm.
Tetsuo Endoh - One of the best experts on this subject based on the ideXlab platform.
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Nonvolatile Low Power 16-Bit/32-Bit Magnetic Tunnel Junction Based Binary Counter and Its Scaling
Japanese Journal of Applied Physics, 2012Co-Authors: Shuta Togashi, Takashi Ohsawa, Tetsuo EndohAbstract:We propose a nonvolatile 16-Bit/32-Bit magnetic tunnel junction (MTJ) based binary Counter with fine-grained power gating scheme suitable for MTJ. We estimate the power consumption of the proposed Counter by using simulation program with integrated circuit emphasis (SPICE) simulation. The power of the proposed 16-Bit/32-Bit Counter is 59.1 and 72.5% smaller in case of 45 and 16 nm node, respectively, than that of the conventional complementary metal oxide semiconductor (CMOS) Counter at low frequency (100 Hz). The proposed nonvolatile 32-Bit Counter achieves lower power at operating frequencies up to 49 kHz and 4 MHz in the case of 45 and 16 nm node, respectively, in comparison with the conventional CMOS Counter. Moreover, we propose a hybrid 32-Bit Counter that is constructed with CMOS Counter units for the beginning stages and nonvolatile MTJ based Counter units for the latter stages. It achieves a lower power at operating frequencies up to 1 GHz than the conventional CMOS Counter for 16 nm node. As a result, clear scalability of the proposed MTJ based multi-Bit Counter is obtained from the viewpoint of suppressing power.
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nonvolatile low power 16 Bit 32 Bit magnetic tunnel junction based binary Counter and its scaling
Japanese Journal of Applied Physics, 2012Co-Authors: Shuta Togashi, Takashi Ohsawa, Tetsuo EndohAbstract:We propose a nonvolatile 16-Bit/32-Bit magnetic tunnel junction (MTJ) based binary Counter with fine-grained power gating scheme suitable for MTJ. We estimate the power consumption of the proposed Counter by using simulation program with integrated circuit emphasis (SPICE) simulation. The power of the proposed 16-Bit/32-Bit Counter is 59.1 and 72.5% smaller in case of 45 and 16 nm node, respectively, than that of the conventional complementary metal oxide semiconductor (CMOS) Counter at low frequency (100 Hz). The proposed nonvolatile 32-Bit Counter achieves lower power at operating frequencies up to 49 kHz and 4 MHz in the case of 45 and 16 nm node, respectively, in comparison with the conventional CMOS Counter. Moreover, we propose a hybrid 32-Bit Counter that is constructed with CMOS Counter units for the beginning stages and nonvolatile MTJ based Counter units for the latter stages. It achieves a lower power at operating frequencies up to 1 GHz than the conventional CMOS Counter for 16 nm node. As a result, clear scalability of the proposed MTJ based multi-Bit Counter is obtained from the viewpoint of suppressing power.