The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform
Keshab K. Parhi - One of the best experts on this subject based on the ideXlab platform.
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calculation of minimum number of registers in 2 d discrete wavelet transforms using lapped Block Processing
International Symposium on Circuits and Systems, 1994Co-Authors: T C Denk, Keshab K. ParhiAbstract:This paper considers architecture design of lapped Block Processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform. >
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ICASSP (1) - Block Processing for rank order filtering using the rank order state machine architecture
IEEE International Conference on Acoustics Speech and Signal Processing, 1993Co-Authors: L.e. Lucke, Keshab K. ParhiAbstract:Rank order filters are nonlinear filters which choose an output based on its rank within a one-dimensional window of sample inputs determined by sorting the inputs. These filters are constructed using running order sorter architectures which utilize the overlap between consecutive outputs to maintain a sorted list of the inputs within the sample window. Additional speedup can be achieved in the rank order filter structures using Block Processing techniques. Block Processing transforms a single-input single-output structure into a parallel-input parallel-output structure. It is difficult to apply Block Processing to most running order sorters because of the inherent feedback in their structures. A new class two architecture for rank order filtering, the rank order state machine, has been introduced. The authors discuss how Block Processing can be effectively applied to the rank order state machine architecture. They also extend this architecture to support Block structures for stack filtering. Several architectures for rank order filtering and stack filtering using the rank order state machine architecture are presented. >
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ISCAS - Calculation of minimum number of registers in 2-D discrete wavelet transforms using lapped Block Processing
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94, 1Co-Authors: T C Denk, Keshab K. ParhiAbstract:This paper considers architecture design of lapped Block Processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform. >
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Two-dimensional recursive digital filtering: pipelining, one- and two-dimensional Block Processing
1988. IEEE International Symposium on Circuits and Systems, 1Co-Authors: Keshab K. Parhi, David G. MesserschmittAbstract:Unlike one-dimensional recursive systems, two-dimensional recursive digital filter algorithms possess a large amount of inherent concurrency which can be exploited for pipelining and/or parallelism. The locus of these concurrent computations is referred to as the concurrent computation region. The authors describe the use of this concurrency to derive pipelined and one-dimensional Block architecture for implementation of two-dimensional recursive digital filters by appropriate interleaving (or indexing) of the input samples, without requiring any algorithm transformation and without any hardware overhead. They also derive a two-dimensional incremental Block filter using look-ahead computation and incremental computation techniques. Pipelined two-dimensional Block structures and the index mapping functions for various architectures are presented. Finally, it is shown that for an N-dimensional recursive filter, the concurrent computation region corresponds to an (N-1)-dimensional hyperplane. >
Meenakshi Kaul - One of the best experts on this subject based on the ideXlab platform.
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Design-Space Exploration for Block-Processing Based TemporalPartitioning of Run-Time Reconfigurable Systems
2000Co-Authors: Meenakshi Kaul, Ranga VemuriAbstract:The reconfiguration capability of modern FPGA devices can be utilized to execute an application by partitioning it into multiple segments such that each segment is executed one after the other on the device. This division of an application into multiple reconfigurable segments is called temporal partitioning. We present an automated temporal partitioning technique for acyclic behavior level task graphs. To be effective, any behavior-level partitioning method should ensure that each temporal partition meets the underlying resource constraints. For this, a knowledge of the implementation cost of each task on the hardware should be known. Since multiple implementations of a task that differ in area and delay are possible, we perform design-space exploration to choose the best implementation of a task from among the available implementations. To overcome the high reconfiguration overhead of the current day FPGA devices, we propose integration of the temporal partitioning and design space exploration methodology with Block-Processing. Block-Processing is used to process multiple Blocks of data on each temporal partition so as to amortize the reconfiguration time. We focus on applications that can be represented as task graphs that have to be executed many times over a large set of input data. We have integrated Block-Processing in the temporal partitioning framework so that it also influences the design point selection for each task. However, this does not exclude usage of our system for designs for which Block-Processing is not possible. For both Block-Processing and non Block-Processing designs our algorithm selects the best possible design point to minimize the execution time of the design. We present an ILP-based methodology for the integrated temporal partitioning, design space exploration and Block-Processing technique that is solved to optimality for small sized design problems and in an iterative constraint satisfaction approach for large sized design problems. We demonstrate with extensive experimental results for the Discrete Cosine Transform (DCT) and random graphs the validity of our approach.
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Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems
Journal of VLSI signal processing systems for signal image and video technology, 2000Co-Authors: Meenakshi Kaul, Ranga VemuriAbstract:The reconfiguration capability of modern FPGA devices can be utilized to execute an application by partitioning it into multiple segments such that each segment is executed one after the other on the device. This division of an application into multiple reconfigurable segments is called temporal partitioning. We present an automated temporal partitioning technique for acyclic behavior level task graphs. To be effective, any behavior-level partitioning method should ensure that each temporal partition meets the underlying resource constraints. For this, a knowledge of the implementation cost of each task on the hardware should be known. Since multiple implementations of a task that differ in area and delay are possible, we perform design-space exploration to choose the best implementation of a task from among the available implementations. To overcome the high reconfiguration overhead of the current day FPGA devices, we propose integration of the temporal partitioning and design space exploration methodology with Block-Processing. Block-Processing is used to process multiple Blocks of data on each temporal partition so as to amortize the reconfiguration time. We focus on applications that can be represented as task graphs that have to be executed many times over a large set of input data. We have integrated Block-Processing in the temporal partitioning framework so that it also influences the design point selection for each task. However, this does not exclude usage of our system for designs for which Block-Processing is not possible. For both Block-Processing and non Block-Processing designs our algorithm selects the best possible design point to minimize the execution time of the design. We present an ILP-based methodology for the integrated temporal partitioning, design space exploration and Block-Processing technique that is solved to optimality for small sized design problems and in an iterative constraint satisfaction approach for large sized design problems. We demonstrate with extensive experimental results for the Discrete Cosine Transform (DCT) and random graphs the validity of our approach.
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IPPS/SPDP Workshops - Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures
Lecture Notes in Computer Science, 1999Co-Authors: Meenakshi Kaul, Ranga VermuriAbstract:We present an automated temporal partitioning and design space exploration methodology that temporally partitions behavior specifications. We propose Block-Processing in the temporal partitioning framework for reducing the reconfiguration overhead for partitioned designs. Block-Processing is a technique used traditionally in the area of parallel compilers, for increasing the computation speed by Processing several inputs simultaneously. Block-Processing technique has been integrated with task-level design space exploration to achieve designs that justify temporal partitioning of systems. An ILP-based methodology has been proposed to solve this problem. We present experimental results for the Discrete Cosine Transform (DCT).
Tae-sun Choi - One of the best experts on this subject based on the ideXlab platform.
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Accurate Registration Using Adaptive Block Processing for Multispectral Images
IEEE Transactions on Circuits and Systems for Video Technology, 2013Co-Authors: Ik Hyun Lee, Tae-sun ChoiAbstract:Image registration is a challenging task, with applications in surveillance, motion estimation, and fusion systems. Due to the diversity of sensors, local distortions and large image size, satellite images are often difficult to accurately register. In the literature, local descriptor-based Processing techniques, such as scale-invariant feature transforms (SIAdaptive Block ProcessingFTs), have been applied to register satellite images, which provide robust features. However, these techniques suffer from a high-computational cost, lack of features, and low-distribution quality, which affect the registration accuracy. In this paper, we develop an algorithm to register satellite images based on adaptive Block Processing to increase the number of features and to improve the distribution quality. In addition, outlier removal using statistical masks are associated with classical random sample consensus (RANSAC); a subsequent comparative analysis demonstrates the accuracy of the proposed method. Typically, a classical SIFT prevents its wide application in recent remote sensing, although this is no longer the case with the proposed adaptive Block Processing method.
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Entropy-Based Block Processing for Satellite Image Registration
Entropy, 2012Co-Authors: Ik Hyun Lee, Doo-chun Seo, Tae-sun ChoiAbstract:Image registration is an important task in many computer vision applications such as fusion systems, 3D shape recovery and earth observation. Particularly, registering satellite images is challenging and time-consuming due to limited resources and large image size. In such scenario, state-of-the-art image registration methods such as scale-invariant feature transform (SIFT) may not be suitable due to high Processing time. In this paper, we propose an algorithm based on Block Processing via entropy to register satellite images. The performance of the proposed method is evaluated using different real images. The comparative analysis shows that it not only reduces the Processing time but also enhances the accuracy.
Ik Hyun Lee - One of the best experts on this subject based on the ideXlab platform.
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Accurate Registration Using Adaptive Block Processing for Multispectral Images
IEEE Transactions on Circuits and Systems for Video Technology, 2013Co-Authors: Ik Hyun Lee, Tae-sun ChoiAbstract:Image registration is a challenging task, with applications in surveillance, motion estimation, and fusion systems. Due to the diversity of sensors, local distortions and large image size, satellite images are often difficult to accurately register. In the literature, local descriptor-based Processing techniques, such as scale-invariant feature transforms (SIAdaptive Block ProcessingFTs), have been applied to register satellite images, which provide robust features. However, these techniques suffer from a high-computational cost, lack of features, and low-distribution quality, which affect the registration accuracy. In this paper, we develop an algorithm to register satellite images based on adaptive Block Processing to increase the number of features and to improve the distribution quality. In addition, outlier removal using statistical masks are associated with classical random sample consensus (RANSAC); a subsequent comparative analysis demonstrates the accuracy of the proposed method. Typically, a classical SIFT prevents its wide application in recent remote sensing, although this is no longer the case with the proposed adaptive Block Processing method.
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Entropy-Based Block Processing for Satellite Image Registration
Entropy, 2012Co-Authors: Ik Hyun Lee, Doo-chun Seo, Tae-sun ChoiAbstract:Image registration is an important task in many computer vision applications such as fusion systems, 3D shape recovery and earth observation. Particularly, registering satellite images is challenging and time-consuming due to limited resources and large image size. In such scenario, state-of-the-art image registration methods such as scale-invariant feature transform (SIFT) may not be suitable due to high Processing time. In this paper, we propose an algorithm based on Block Processing via entropy to register satellite images. The performance of the proposed method is evaluated using different real images. The comparative analysis shows that it not only reduces the Processing time but also enhances the accuracy.
Ranga Vermuri - One of the best experts on this subject based on the ideXlab platform.
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IPPS/SPDP Workshops - Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures
Lecture Notes in Computer Science, 1999Co-Authors: Meenakshi Kaul, Ranga VermuriAbstract:We present an automated temporal partitioning and design space exploration methodology that temporally partitions behavior specifications. We propose Block-Processing in the temporal partitioning framework for reducing the reconfiguration overhead for partitioned designs. Block-Processing is a technique used traditionally in the area of parallel compilers, for increasing the computation speed by Processing several inputs simultaneously. Block-Processing technique has been integrated with task-level design space exploration to achieve designs that justify temporal partitioning of systems. An ILP-based methodology has been proposed to solve this problem. We present experimental results for the Discrete Cosine Transform (DCT).