The Experts below are selected from a list of 5325 Experts worldwide ranked by ideXlab platform
Lieven Eeckhout - One of the best experts on this subject based on the ideXlab platform.
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thread similarity matrix visualizing Branch Divergence in gpgpu programs
International Conference on Parallel Processing, 2016Co-Authors: Lieven EeckhoutAbstract:Graphics processing units (GPUs) have recently evolved into popular accelerators for general-purpose parallel programs -- so-called GPGPU computing. Although programming models such as CUDA and OpenCL significantly improve GPGPU programmability, optimizing GPGPU programs is still far from trivial. Branch Divergence is one of the root causes reducing GPGPU performance. Existing approaches are able to calculate the Branch Divergence rate but are unable to reveal how the Branches diverge in a GPGPU program. In this paper, we propose the Thread Similarity Matrix (TSM) to visualize how Branches diverge and in turn help find optimization opportunities. TSM contains an element for each pair of threads, representing the difference in code being executed by the pair of threads. The darker the element, the more similar the threads are, the lighter, the more dissimilar. TSM therefore allows GPGPU programmers to easily understand an application's Branch Divergence behavior and pinpoint performance anomalies. We present a case study to demonstrate how TSM can help optimize GPGPU programs: we improve the performance of a highly-optimized GPGPU kernel by 35% by reorganizing its thread organization to reduce its Branch Divergence rate.
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ICPP - Thread Similarity Matrix: Visualizing Branch Divergence in GPGPU Programs
2016 45th International Conference on Parallel Processing (ICPP), 2016Co-Authors: Lieven EeckhoutAbstract:Graphics processing units (GPUs) have recently evolved into popular accelerators for general-purpose parallel programs -- so-called GPGPU computing. Although programming models such as CUDA and OpenCL significantly improve GPGPU programmability, optimizing GPGPU programs is still far from trivial. Branch Divergence is one of the root causes reducing GPGPU performance. Existing approaches are able to calculate the Branch Divergence rate but are unable to reveal how the Branches diverge in a GPGPU program. In this paper, we propose the Thread Similarity Matrix (TSM) to visualize how Branches diverge and in turn help find optimization opportunities. TSM contains an element for each pair of threads, representing the difference in code being executed by the pair of threads. The darker the element, the more similar the threads are, the lighter, the more dissimilar. TSM therefore allows GPGPU programmers to easily understand an application's Branch Divergence behavior and pinpoint performance anomalies. We present a case study to demonstrate how TSM can help optimize GPGPU programs: we improve the performance of a highly-optimized GPGPU kernel by 35% by reorganizing its thread organization to reduce its Branch Divergence rate.
Weichung Hsu - One of the best experts on this subject based on the ideXlab platform.
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a pipeline based heterogeneous framework for efficient synthetic light field rendering
ACM Sigapp Applied Computing Review, 2018Co-Authors: Chihchen Kao, Liangchi Tseng, Weichung HsuAbstract:The research interest of real-time global illumination has increased due to the growing demand of graphics applications such as virtual reality. Recently, the design that combines Image-Based Rendering (IBR) and Ray-Tracing to create Synthetic Light Field (SLF) has been widely adopted to provide delicate visual experience for multiple viewpoints at an acceptable frame rate. However, despite its parallel characteristic, constructing a SLF is still inefficient on modern Graphics Processing Unit (GPU) due to the irregularities. For instance, the issues caused by Branch Divergence, early-termination and irregular memory access prolong the execution time that cannot be simply resolved by workload merging. In this paper, we proposed a Runtime framework that reorganizes the execution into a pipeline-based pattern with grouping of primary rays. The workloads are later distributed to all heterogeneous cores to increase the efficiency of the execution. With this approach, the number of valid rays can be maintained at a high level with less Divergence of paths. Based on the experiment on a heterogeneous system, the maximum throughput for a single GPU becomes 3.12 times higher than the original on average and becomes even higher on systems with multiple heterogeneous cores.
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efficient synthetic light field rendering on heterogeneous systems using a pipeline based runtime design
Research in Adaptive and Convergent Systems, 2017Co-Authors: Chihchen Kao, Liangchi Tseng, Weichung HsuAbstract:The research interest of real-time global illumination has increased due to the growing demand of graphics applications such as virtual reality. Recently, the design that combines Image-based rendering (IBR) and Ray-Tracing to create Synthetic Light Field (SLF) has been widely adopted to provide delicate visual experience for multiple viewpoints at an acceptable frame rate. However, despite its parallel characteristic, constructing a SLF is still inefficient on modern Graphics Processing Unit (GPU) due to the irregularities. For instance, the issues caused by Branch Divergence, early-termination and irregular memory access prolong the execution time that cannot be simply resolved by workload merging. In this paper, we proposed a Runtime design that reorganizes the execution into a pipeline-based pattern with grouping of primary rays. With this approach, the number of valid rays can be maintained at a high level with less Divergence of paths. Based on the experiment on a heterogeneous system, the throughput becomes 2.48 times higher than the original on average.
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RACS - Efficient Synthetic Light Field Rendering on Heterogeneous Systems Using a Pipeline-Based Runtime Design
Proceedings of the International Conference on Research in Adaptive and Convergent Systems, 2017Co-Authors: Chihchen Kao, Liangchi Tseng, Weichung HsuAbstract:The research interest of real-time global illumination has increased due to the growing demand of graphics applications such as virtual reality. Recently, the design that combines Image-based rendering (IBR) and Ray-Tracing to create Synthetic Light Field (SLF) has been widely adopted to provide delicate visual experience for multiple viewpoints at an acceptable frame rate. However, despite its parallel characteristic, constructing a SLF is still inefficient on modern Graphics Processing Unit (GPU) due to the irregularities. For instance, the issues caused by Branch Divergence, early-termination and irregular memory access prolong the execution time that cannot be simply resolved by workload merging. In this paper, we proposed a Runtime design that reorganizes the execution into a pipeline-based pattern with grouping of primary rays. With this approach, the number of valid rays can be maintained at a high level with less Divergence of paths. Based on the experiment on a heterogeneous system, the throughput becomes 2.48 times higher than the original on average.
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ICME - A pipeline-based runtime technique for improving Ray-Tracing on HSA-compliant systems
2016 IEEE International Conference on Multimedia and Expo (ICME), 2016Co-Authors: Chihchen Kao, Yu-tsung Miao, Weichung HsuAbstract:The prevalence of real time multimedia delivery appliances has led to the developments of a variety of efficient architectures and supporting software technologies. Especially, Ray-Tracing, a well-known physically-based rendering algorithm, has been receiving great attention in research and development. Unfortunately, Ray-Tracing algorithm, being one of the irregular applications, suffers from the performance penalty on SIMT-based machines such as GPGPUs. Specifically, the Branch Divergence and early-termination issues caused by the irregularity severely degrade the overall hardware utilization, which makes the computation on GPGPU inefficient while traversing through each iterative stages of the algorithm. The probabilistic termination of ray-tracing paths poses a critical issue for efficient parallel execution on GPGPUs. Moreover, the conventional overhead of memory transfer limits the effectiveness of data marshaling for GPU computing. To address these problems, we proposed a pipeline-based Runtime technique which leverages the feature of Shared-Virtual-Memory (SVM) of the HSA-compliant systems that combines and regroups the workload from different stages into one kernel computation in Ray-Tracing and greatly improved the resource utilization of GPGPU. Our experiments illustrate that the proposed runtime technique can boost ray-tracing performance significantly while effectively increase the utilization of HSA-compliant heterogeneous systems.
Chihchen Kao - One of the best experts on this subject based on the ideXlab platform.
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a pipeline based heterogeneous framework for efficient synthetic light field rendering
ACM Sigapp Applied Computing Review, 2018Co-Authors: Chihchen Kao, Liangchi Tseng, Weichung HsuAbstract:The research interest of real-time global illumination has increased due to the growing demand of graphics applications such as virtual reality. Recently, the design that combines Image-Based Rendering (IBR) and Ray-Tracing to create Synthetic Light Field (SLF) has been widely adopted to provide delicate visual experience for multiple viewpoints at an acceptable frame rate. However, despite its parallel characteristic, constructing a SLF is still inefficient on modern Graphics Processing Unit (GPU) due to the irregularities. For instance, the issues caused by Branch Divergence, early-termination and irregular memory access prolong the execution time that cannot be simply resolved by workload merging. In this paper, we proposed a Runtime framework that reorganizes the execution into a pipeline-based pattern with grouping of primary rays. The workloads are later distributed to all heterogeneous cores to increase the efficiency of the execution. With this approach, the number of valid rays can be maintained at a high level with less Divergence of paths. Based on the experiment on a heterogeneous system, the maximum throughput for a single GPU becomes 3.12 times higher than the original on average and becomes even higher on systems with multiple heterogeneous cores.
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efficient synthetic light field rendering on heterogeneous systems using a pipeline based runtime design
Research in Adaptive and Convergent Systems, 2017Co-Authors: Chihchen Kao, Liangchi Tseng, Weichung HsuAbstract:The research interest of real-time global illumination has increased due to the growing demand of graphics applications such as virtual reality. Recently, the design that combines Image-based rendering (IBR) and Ray-Tracing to create Synthetic Light Field (SLF) has been widely adopted to provide delicate visual experience for multiple viewpoints at an acceptable frame rate. However, despite its parallel characteristic, constructing a SLF is still inefficient on modern Graphics Processing Unit (GPU) due to the irregularities. For instance, the issues caused by Branch Divergence, early-termination and irregular memory access prolong the execution time that cannot be simply resolved by workload merging. In this paper, we proposed a Runtime design that reorganizes the execution into a pipeline-based pattern with grouping of primary rays. With this approach, the number of valid rays can be maintained at a high level with less Divergence of paths. Based on the experiment on a heterogeneous system, the throughput becomes 2.48 times higher than the original on average.
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RACS - Efficient Synthetic Light Field Rendering on Heterogeneous Systems Using a Pipeline-Based Runtime Design
Proceedings of the International Conference on Research in Adaptive and Convergent Systems, 2017Co-Authors: Chihchen Kao, Liangchi Tseng, Weichung HsuAbstract:The research interest of real-time global illumination has increased due to the growing demand of graphics applications such as virtual reality. Recently, the design that combines Image-based rendering (IBR) and Ray-Tracing to create Synthetic Light Field (SLF) has been widely adopted to provide delicate visual experience for multiple viewpoints at an acceptable frame rate. However, despite its parallel characteristic, constructing a SLF is still inefficient on modern Graphics Processing Unit (GPU) due to the irregularities. For instance, the issues caused by Branch Divergence, early-termination and irregular memory access prolong the execution time that cannot be simply resolved by workload merging. In this paper, we proposed a Runtime design that reorganizes the execution into a pipeline-based pattern with grouping of primary rays. With this approach, the number of valid rays can be maintained at a high level with less Divergence of paths. Based on the experiment on a heterogeneous system, the throughput becomes 2.48 times higher than the original on average.
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ICME - A pipeline-based runtime technique for improving Ray-Tracing on HSA-compliant systems
2016 IEEE International Conference on Multimedia and Expo (ICME), 2016Co-Authors: Chihchen Kao, Yu-tsung Miao, Weichung HsuAbstract:The prevalence of real time multimedia delivery appliances has led to the developments of a variety of efficient architectures and supporting software technologies. Especially, Ray-Tracing, a well-known physically-based rendering algorithm, has been receiving great attention in research and development. Unfortunately, Ray-Tracing algorithm, being one of the irregular applications, suffers from the performance penalty on SIMT-based machines such as GPGPUs. Specifically, the Branch Divergence and early-termination issues caused by the irregularity severely degrade the overall hardware utilization, which makes the computation on GPGPU inefficient while traversing through each iterative stages of the algorithm. The probabilistic termination of ray-tracing paths poses a critical issue for efficient parallel execution on GPGPUs. Moreover, the conventional overhead of memory transfer limits the effectiveness of data marshaling for GPU computing. To address these problems, we proposed a pipeline-based Runtime technique which leverages the feature of Shared-Virtual-Memory (SVM) of the HSA-compliant systems that combines and regroups the workload from different stages into one kernel computation in Ray-Tracing and greatly improved the resource utilization of GPGPU. Our experiments illustrate that the proposed runtime technique can boost ray-tracing performance significantly while effectively increase the utilization of HSA-compliant heterogeneous systems.
Leesup Kim - One of the best experts on this subject based on the ideXlab platform.
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a reconfigurable simt processor for mobile ray tracing with contention reduction in shared memory
IEEE Transactions on Circuits and Systems, 2013Co-Authors: Hongyun Kim, Youngjun Kim, Leesup KimAbstract:In this paper, we present a reconfigurable SIMT multi-core processor with a shared memory for mobile ray tracing. The proposed processor addresses two issues of SIMT architecture: Branch Divergence of concurrently executed threads and contention in a shared memory. Performance degradation due to the Branch Divergence is reduced by dividing a wide SIMT datapath into several narrow SIMT cores that execute independent threads asynchronously. The contention in a shared memory caused by the multiple SIMT cores is alleviated by introducing a new time-division multiplexing (TDM) scheme using multi-phase clocks. The SIMT cores send their requests to a shared memory sequentially not concurrently by synchronizing the SIMT cores with multi-phase clocks to hide arbitration delays. The processor achieves the same datapath utilization as 4-wide SIMT which has been widely used by CPU-based ray tracers while its area remains 68% of the 4-wide SIMT. As a result, the performance normalized to area is improved by 26% compared to previous work with negligible overheads (2.6% for area and 1% for power consumption). The chip was fabricated in 90 nm CMOS technology, and it contains 2.3 M logic gates and 19.3 KB SRAM. It consumes 221 mW at 100 MHz with Vdd=1.2 V.
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MRTP: Mobile Ray Tracing Processor With Reconfigurable Stream Multi-Processors for High Datapath Utilization
IEEE Journal of Solid-State Circuits, 2012Co-Authors: Hongyun Kim, Youngjun Kim, Leesup KimAbstract:This paper presents a mobile ray tracing processor (MRTP) with reconfigurable stream multi-processors (RSMPs) for high datapath utilization. The MRTP includes three RSMPs that operate in multiple instruction multiple data (MIMD) mode asynchronously to exploit instruction-level parallelism. Each RSMP is based on single instruction multiple thread (SIMT) architecture to exploit thread-level parallelism. An RSMP consists of twelve scalar processing elements (SPEs) that run multiple threads in parallel synchronously: twelve scalar threads or four vector threads depending on an operating mode. A low datapath utilization caused by a Branch Divergence in SIMT architecture is improved by 19.9% on average by reconfiguring twelve SPEs between scalar SIMT and vector SIMT with 0.1% area overheads. Special function instructions occupy only 2% ~ 8% of kernel instructions so that a partial special function unit (PSFU) is implemented instead of a large dedicated SFU. The access conflicts with a look-up table (LUT) caused by concurrent accesses of twelve SPEs are reduced by a table loader (TBLD). The TBLD monitors concurrent requests from twelve SPEs and reduces an access count to LUT by distributing a coefficient to multiple SPEs with only one read-access to LUT. MRTP with area of 4 × 4 mm2 has been fabricated in 0.13 μm CMOS technology. MRTP achieves a peak performance of 673 K rays per second while consuming 156 mW at 100 MHz with VDD = 1.2 V .
Paolo Ienne - One of the best experts on this subject based on the ideXlab platform.
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High performance comparison-based sorting algorithm on many-core GPUs
2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), 2010Co-Authors: Xiaochun Ye, Nan Yuan, Paolo IenneAbstract:Sorting is a kernel algorithm for a wide range of applications. In this paper, we present a new algorithm, GPU-Warpsort, to perform comparison-based parallel sort on Graphics Processing Units (GPUs). It mainly consists of a bitonic sort followed by a merge sort. Our algorithm achieves high performance by efficiently mapping the sorting tasks to GPU architectures. Firstly, we take advantage of the synchronous execution of threads in a warp to eliminate the barriers in bitonic sorting network. We also provide sufficient homogeneous parallel operations for all the threads within a warp to avoid Branch Divergence. Furthermore, we implement the merge sort efficiently by assigning each warp independent pairs of sequences to be merged and by exploiting totally coalesced global memory accesses to eliminate the bandwidth bottleneck. Our experimental results indicate that GPU-Warpsort works well on different kinds of input distributions, and it achieves up to 30% higher performance than previous optimized comparison-based GPU sorting algorithm on input sequences with millions of elements.
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high performance comparison based sorting algorithm on many core gpus
International Parallel and Distributed Processing Symposium, 2010Co-Authors: Xiaochun Ye, Nan Yuan, Paolo IenneAbstract:Sorting is a kernel algorithm for a wide range of applications. We present a new algorithm, GPU-Warpsort, to perform comparison-based parallel sort on Graphics Processing Units (GPUs). It mainly consists of a bitonic sort followed by a merge sort. Our algorithm achieves high performance by efficiently mapping the sorting tasks to GPU architectures. Firstly, we take advantage of the synchronous execution of threads in a warp to eliminate the barriers in bitonic sorting network. We also provide sufficient homogeneous parallel operations for all the threads within a warp to avoid Branch Divergence. Furthermore, we implement the merge sort efficiently by assigning each warp independent pairs of sequences to be merged and by exploiting totally coalesced global memory accesses to eliminate the bandwidth bottleneck. Our experimental results indicate that GPU-Warpsort works well on different kinds of input distributions, and it achieves up to 30% higher performance than previous optimized comparison-based GPU sorting algorithm on input sequences with millions of elements.
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IPDPS - High performance comparison-based sorting algorithm on many-core GPUs
2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), 2010Co-Authors: Dongrui Fan, Nan Yuan, Wei Lin, Paolo IenneAbstract:Sorting is a kernel algorithm for a wide range of applications. We present a new algorithm, GPU-Warpsort, to perform comparison-based parallel sort on Graphics Processing Units (GPUs). It mainly consists of a bitonic sort followed by a merge sort. Our algorithm achieves high performance by efficiently mapping the sorting tasks to GPU architectures. Firstly, we take advantage of the synchronous execution of threads in a warp to eliminate the barriers in bitonic sorting network. We also provide sufficient homogeneous parallel operations for all the threads within a warp to avoid Branch Divergence. Furthermore, we implement the merge sort efficiently by assigning each warp independent pairs of sequences to be merged and by exploiting totally coalesced global memory accesses to eliminate the bandwidth bottleneck. Our experimental results indicate that GPU-Warpsort works well on different kinds of input distributions, and it achieves up to 30% higher performance than previous optimized comparison-based GPU sorting algorithm on input sequences with millions of elements.