The Experts below are selected from a list of 8037 Experts worldwide ranked by ideXlab platform
Shobha Vasudevan - One of the best experts on this subject based on the ideXlab platform.
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application level hardware tracing for scaling post silicon debug
Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model specifications of interacting flows in typical applications. Our method optimizes trace Buffer Utilization and flow specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace Buffer Utilization of 98.96% with a flow specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
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DAC - Application level hardware tracing for scaling post-silicon debug
Proceedings of the 55th Annual Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model specifications of interacting flows in typical applications. Our method optimizes trace Buffer Utilization and flow specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace Buffer Utilization of 98.96% with a flow specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
Christoph Laroque - One of the best experts on this subject based on the ideXlab platform.
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Buffer Utilization based scheduling of maintenance activities by a shifting priority approach a simulation study
Winter Simulation Conference, 2016Co-Authors: Maheshwaran Gopalakrishnan, Anders Skoogh, Christoph LaroqueAbstract:Machine breakdowns and improper maintenance management cause production systems to function inefficiently. Particularly, breakdowns cause rippling effects on other machines in terms of starved and blocked states. Effective planning of maintenance can lead to improved production system efficiency. This paper aims at improving system throughput through prioritization of maintenance work orders by continuously monitoring Buffer levels. This paper proposes and tests a new approach to determine the machine priorities for dynamic scheduling of maintenance work orders by identifying Buffer Utilization. The approach is exemplified in an industrial use-case. The results have shown to increase throughput in comparison to a first-come-first-served approach for executing maintenance work orders. This new approach relies on simple data collection and analysis, which makes it a viable option for industries to implement with minimal effort. The results can suggest that systems view for maintenance prioritization can be a powerful decision support tool for maintenance planning.
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Winter Simulation Conference - Buffer Utilization based scheduling of maintenance activities by a shifting priority approach: a simulation study
2016 Winter Simulation Conference (WSC), 2016Co-Authors: Maheshwaran Gopalakrishnan, Anders Skoogh, Christoph LaroqueAbstract:Machine breakdowns and improper maintenance management cause production systems to function inefficiently. Particularly, breakdowns cause rippling effects on other machines in terms of starved and blocked states. Effective planning of maintenance can lead to improved production system efficiency. This paper aims at improving system throughput through prioritization of maintenance work orders by continuously monitoring Buffer levels. This paper proposes and tests a new approach to determine the machine priorities for dynamic scheduling of maintenance work orders by identifying Buffer Utilization. The approach is exemplified in an industrial use-case. The results have shown to increase throughput in comparison to a first-come-first-served approach for executing maintenance work orders. This new approach relies on simple data collection and analysis, which makes it a viable option for industries to implement with minimal effort. The results can suggest that systems view for maintenance prioritization can be a powerful decision support tool for maintenance planning.
Debjit Pal - One of the best experts on this subject based on the ideXlab platform.
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application level hardware tracing for scaling post silicon debug
Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model specifications of interacting flows in typical applications. Our method optimizes trace Buffer Utilization and flow specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace Buffer Utilization of 98.96% with a flow specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
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DAC - Application level hardware tracing for scaling post-silicon debug
Proceedings of the 55th Annual Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model specifications of interacting flows in typical applications. Our method optimizes trace Buffer Utilization and flow specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace Buffer Utilization of 98.96% with a flow specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
Maheshwaran Gopalakrishnan - One of the best experts on this subject based on the ideXlab platform.
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Buffer Utilization based scheduling of maintenance activities by a shifting priority approach a simulation study
Winter Simulation Conference, 2016Co-Authors: Maheshwaran Gopalakrishnan, Anders Skoogh, Christoph LaroqueAbstract:Machine breakdowns and improper maintenance management cause production systems to function inefficiently. Particularly, breakdowns cause rippling effects on other machines in terms of starved and blocked states. Effective planning of maintenance can lead to improved production system efficiency. This paper aims at improving system throughput through prioritization of maintenance work orders by continuously monitoring Buffer levels. This paper proposes and tests a new approach to determine the machine priorities for dynamic scheduling of maintenance work orders by identifying Buffer Utilization. The approach is exemplified in an industrial use-case. The results have shown to increase throughput in comparison to a first-come-first-served approach for executing maintenance work orders. This new approach relies on simple data collection and analysis, which makes it a viable option for industries to implement with minimal effort. The results can suggest that systems view for maintenance prioritization can be a powerful decision support tool for maintenance planning.
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Winter Simulation Conference - Buffer Utilization based scheduling of maintenance activities by a shifting priority approach: a simulation study
2016 Winter Simulation Conference (WSC), 2016Co-Authors: Maheshwaran Gopalakrishnan, Anders Skoogh, Christoph LaroqueAbstract:Machine breakdowns and improper maintenance management cause production systems to function inefficiently. Particularly, breakdowns cause rippling effects on other machines in terms of starved and blocked states. Effective planning of maintenance can lead to improved production system efficiency. This paper aims at improving system throughput through prioritization of maintenance work orders by continuously monitoring Buffer levels. This paper proposes and tests a new approach to determine the machine priorities for dynamic scheduling of maintenance work orders by identifying Buffer Utilization. The approach is exemplified in an industrial use-case. The results have shown to increase throughput in comparison to a first-come-first-served approach for executing maintenance work orders. This new approach relies on simple data collection and analysis, which makes it a viable option for industries to implement with minimal effort. The results can suggest that systems view for maintenance prioritization can be a powerful decision support tool for maintenance planning.
Abhishek Sharma - One of the best experts on this subject based on the ideXlab platform.
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application level hardware tracing for scaling post silicon debug
Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model specifications of interacting flows in typical applications. Our method optimizes trace Buffer Utilization and flow specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace Buffer Utilization of 98.96% with a flow specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
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DAC - Application level hardware tracing for scaling post-silicon debug
Proceedings of the 55th Annual Design Automation Conference, 2018Co-Authors: Debjit Pal, Abhishek Sharma, Sandip Ray, Flavio M De Paula, Shobha VasudevanAbstract:We present a method for selecting trace messages for post-silicon validation of Systems-on-a-Chips (SoCs) with diverse usage scenarios. We model specifications of interacting flows in typical applications. Our method optimizes trace Buffer Utilization and flow specification coverage. We present debugging and root cause analysis of subtle bugs in the industry scale OpenSPARC T2 processor. We demonstrate that this scale is beyond the capacity of current tracing approaches. We achieve trace Buffer Utilization of 98.96% with a flow specification coverage of 94.3% (average). We localize bugs to 21.11% (average) of the potential root causes in our large-scale debugging effort.
