The Experts below are selected from a list of 3402549 Experts worldwide ranked by ideXlab platform
James Hofmeister - One of the best experts on this subject based on the ideXlab platform.
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Statistical pattern recognition and Built-in reliability test for feature extraction and health monitoring of electronics under shock loads
2009Co-Authors: Pradeep Lall, Priyanka Choudhary, Sameep Gupte, James HofmeisterAbstract:The Built-in Stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses on the pre- failure space and methodologies for quantification of failure in electronic equipment subject to shock and vibration loads using the dynamic response of the electronic equipment. The presented methodologies are applicable at the system level for the identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder- interconnect Built-in reliability test, FFT-based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint Built-in reliability test has been developed for detecting high resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the time-frequency analysis has been used to study the energy densities of the signal in both time and frequency domains, and provide information about the time evolution of frequency content of transient- strain signal. Closed-form models and explicit finite-element models have been developed for the eigen frequencies, mode shapes, and transient response of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data fr-\nom modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock damage to subtle changes in boundary conditions,effective flexural rigidity, and transient strain response has been quantified.
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statistical pattern recognition and built in reliability test for feature extraction and health monitoring of electronics under shock loads
2007Co-Authors: Pradeep Lall, Priyanka Choudhary, Sameep Gupte, Jeffrey C Suhling, James HofmeisterAbstract:The Built-in Stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses is on the pre-failure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder-interconnect Built-in reliability test, FFT based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint Built-in-reliability-test has been developed for detecting high-resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the Time Frequency Analysis has been used to study of the energy densities of the signal in both time and frequency domain, and provide information about the time-evolution of frequency content of transient-strain signal. Closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure. This allows the physical quantification of solder ball crack damage in the form of confidence values and provides a damage index that can be utilized for the health monitoring of solder interconnects in an electronic assembly.
Pradeep Lall - One of the best experts on this subject based on the ideXlab platform.
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Statistical pattern recognition and Built-in reliability test for feature extraction and health monitoring of electronics under shock loads
2009Co-Authors: Pradeep Lall, Priyanka Choudhary, Sameep Gupte, James HofmeisterAbstract:The Built-in Stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses on the pre- failure space and methodologies for quantification of failure in electronic equipment subject to shock and vibration loads using the dynamic response of the electronic equipment. The presented methodologies are applicable at the system level for the identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder- interconnect Built-in reliability test, FFT-based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint Built-in reliability test has been developed for detecting high resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the time-frequency analysis has been used to study the energy densities of the signal in both time and frequency domains, and provide information about the time evolution of frequency content of transient- strain signal. Closed-form models and explicit finite-element models have been developed for the eigen frequencies, mode shapes, and transient response of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data fr-\nom modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock damage to subtle changes in boundary conditions,effective flexural rigidity, and transient strain response has been quantified.
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statistical pattern recognition and built in reliability test for feature extraction and health monitoring of electronics under shock loads
2007Co-Authors: Pradeep Lall, Priyanka Choudhary, Sameep Gupte, Jeffrey C Suhling, James HofmeisterAbstract:The Built-in Stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses is on the pre-failure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder-interconnect Built-in reliability test, FFT based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint Built-in-reliability-test has been developed for detecting high-resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the Time Frequency Analysis has been used to study of the energy densities of the signal in both time and frequency domain, and provide information about the time-evolution of frequency content of transient-strain signal. Closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure. This allows the physical quantification of solder ball crack damage in the form of confidence values and provides a damage index that can be utilized for the health monitoring of solder interconnects in an electronic assembly.
Priyanka Choudhary - One of the best experts on this subject based on the ideXlab platform.
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Statistical pattern recognition and Built-in reliability test for feature extraction and health monitoring of electronics under shock loads
2009Co-Authors: Pradeep Lall, Priyanka Choudhary, Sameep Gupte, James HofmeisterAbstract:The Built-in Stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses on the pre- failure space and methodologies for quantification of failure in electronic equipment subject to shock and vibration loads using the dynamic response of the electronic equipment. The presented methodologies are applicable at the system level for the identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder- interconnect Built-in reliability test, FFT-based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint Built-in reliability test has been developed for detecting high resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the time-frequency analysis has been used to study the energy densities of the signal in both time and frequency domains, and provide information about the time evolution of frequency content of transient- strain signal. Closed-form models and explicit finite-element models have been developed for the eigen frequencies, mode shapes, and transient response of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data fr-\nom modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock damage to subtle changes in boundary conditions,effective flexural rigidity, and transient strain response has been quantified.
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statistical pattern recognition and built in reliability test for feature extraction and health monitoring of electronics under shock loads
2007Co-Authors: Pradeep Lall, Priyanka Choudhary, Sameep Gupte, Jeffrey C Suhling, James HofmeisterAbstract:The Built-in Stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses is on the pre-failure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder-interconnect Built-in reliability test, FFT based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint Built-in-reliability-test has been developed for detecting high-resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the Time Frequency Analysis has been used to study of the energy densities of the signal in both time and frequency domain, and provide information about the time-evolution of frequency content of transient-strain signal. Closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure. This allows the physical quantification of solder ball crack damage in the form of confidence values and provides a damage index that can be utilized for the health monitoring of solder interconnects in an electronic assembly.
Sameep Gupte - One of the best experts on this subject based on the ideXlab platform.
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Statistical pattern recognition and Built-in reliability test for feature extraction and health monitoring of electronics under shock loads
2009Co-Authors: Pradeep Lall, Priyanka Choudhary, Sameep Gupte, James HofmeisterAbstract:The Built-in Stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses on the pre- failure space and methodologies for quantification of failure in electronic equipment subject to shock and vibration loads using the dynamic response of the electronic equipment. The presented methodologies are applicable at the system level for the identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder- interconnect Built-in reliability test, FFT-based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint Built-in reliability test has been developed for detecting high resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the time-frequency analysis has been used to study the energy densities of the signal in both time and frequency domains, and provide information about the time evolution of frequency content of transient- strain signal. Closed-form models and explicit finite-element models have been developed for the eigen frequencies, mode shapes, and transient response of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data fr-\nom modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock damage to subtle changes in boundary conditions,effective flexural rigidity, and transient strain response has been quantified.
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statistical pattern recognition and built in reliability test for feature extraction and health monitoring of electronics under shock loads
2007Co-Authors: Pradeep Lall, Priyanka Choudhary, Sameep Gupte, Jeffrey C Suhling, James HofmeisterAbstract:The Built-in Stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses is on the pre-failure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder-interconnect Built-in reliability test, FFT based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint Built-in-reliability-test has been developed for detecting high-resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the Time Frequency Analysis has been used to study of the energy densities of the signal in both time and frequency domain, and provide information about the time-evolution of frequency content of transient-strain signal. Closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure. This allows the physical quantification of solder ball crack damage in the form of confidence values and provides a damage index that can be utilized for the health monitoring of solder interconnects in an electronic assembly.
Zhigang Suo - One of the best experts on this subject based on the ideXlab platform.
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thermomechanical criteria for overlay alignment in flexible thin film electronic circuits
2006Co-Authors: Helena Gleskova, Chun I Cheng, S Wagner, Zhigang SuoAbstract:A simple mechanical model for a deposited film∕substrate couple is presented to describe how film deposition at an elevated temperature induces change in the substrate’s in-plane dimensions at room temperature. The model provides a quantitative guideline for reducing, or completely eliminating, this elongation, by tailoring the tensile Built-in Stress in the deposited film. The dimensional stability so achieved is necessary for accurate overlay alignment of photomasks during the fabrication of thin-film electronic circuits.
