The Experts below are selected from a list of 3297 Experts worldwide ranked by ideXlab platform
J Tschanz - One of the best experts on this subject based on the ideXlab platform.
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serial link Bus a low power on chip Bus architecture
IEEE Transactions on Circuits and Systems, 2009Co-Authors: Maged Ghoneima, Yehea Ismail, Muhammad M Khellah, J TschanzAbstract:As technology scales, the shrinking wire Width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of Bus lines of the conventional parallel-line Bus (PLB) architecture by multiplexing each m-bits onto a single line. This Bus architecture, the serial-link Bus (SLB), transforms an n-bit conventional PLB into an n/m-line (serial link) Bus. The advantage of SLBs is that they have fewer lines, and if the Bus Width is kept the same, SLBs will have a larger line pitch. Increasing the line Width has a twofold reduction effect on the line resistance; as the resistivity of sub-100 nm wires drops significantly, the line Width increases. Also, increasing the line Width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m opt and an optimum Width to pitch ratio etaopt exist, which minimizes the Bus energy dissipation and maximizes the Bus throughput per unit area. The optimum degree of multiplexing and optimum Width-to-pitch ratio for maximum throughput per unit area and minimum energy dissipation for the 25-130-nm technologies was determined in this paper. Also, an encoding technique was proposed and implemented to reduce the switch activity penalty due to serialization. HSPICE simulations show that for the same throughput per unit area as conventional parallel-line data Buses, the SLB architecture reduces the energy dissipation by up to 31% for a 64-bit Bus implemented in an intermediate metal layer of a 50-nm technology, and a reduction of 53% is projected for a 25-nm technology.
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serial link Bus a low power on chip Bus architecture
International Conference on Computer Aided Design, 2005Co-Authors: Maged Ghoneima, Yehea Ismail, Muhammad M Khellah, J TschanzAbstract:As technology scales, the shrinking wire Width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of Bus lines of the conventional parallel-line Bus CB architecture by multiplexing each m-bits onto a single line. This Bus architecture, the serial-link Bus SLB, transforms an n-bit conventional parallel-line Bus into an n/m-line (serial-link) Bus. The advantage of serial-link Buses is that they have fewer lines, and if the Bus Width is kept the same, serial- link Buses will have larger line Width and spacing. Increasing the line Width has a twofold reduction effect on the line resistance, as the resistivity of sub-100 nm wires significantly drops as the line Width increases. Also, increasing the line Width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m exists that minimizes the Bus energy dissipation and maximizes the Bus throughput per-unit area. The optimum degree of multiplexing for maximum throughput-per- unit-area and for minimum energy dissipation for the 25-130 nm technologies was determined in this paper. HSPICE simulations show that; for the same throughput-per-unit-area as conventional parallel-line Buses, the serial-link Bus architecture reduces the energy dissipation by up to 31.42% for a 64-bit Bus implemented in an intermediate metal layer of a 50 nm technology and a reduction of 52.7% is projected for the 25 nm technology.
Maged Ghoneima - One of the best experts on this subject based on the ideXlab platform.
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serial link Bus a low power on chip Bus architecture
IEEE Transactions on Circuits and Systems, 2009Co-Authors: Maged Ghoneima, Yehea Ismail, Muhammad M Khellah, J TschanzAbstract:As technology scales, the shrinking wire Width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of Bus lines of the conventional parallel-line Bus (PLB) architecture by multiplexing each m-bits onto a single line. This Bus architecture, the serial-link Bus (SLB), transforms an n-bit conventional PLB into an n/m-line (serial link) Bus. The advantage of SLBs is that they have fewer lines, and if the Bus Width is kept the same, SLBs will have a larger line pitch. Increasing the line Width has a twofold reduction effect on the line resistance; as the resistivity of sub-100 nm wires drops significantly, the line Width increases. Also, increasing the line Width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m opt and an optimum Width to pitch ratio etaopt exist, which minimizes the Bus energy dissipation and maximizes the Bus throughput per unit area. The optimum degree of multiplexing and optimum Width-to-pitch ratio for maximum throughput per unit area and minimum energy dissipation for the 25-130-nm technologies was determined in this paper. Also, an encoding technique was proposed and implemented to reduce the switch activity penalty due to serialization. HSPICE simulations show that for the same throughput per unit area as conventional parallel-line data Buses, the SLB architecture reduces the energy dissipation by up to 31% for a 64-bit Bus implemented in an intermediate metal layer of a 50-nm technology, and a reduction of 53% is projected for a 25-nm technology.
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serial link Bus a low power on chip Bus architecture
International Conference on Computer Aided Design, 2005Co-Authors: Maged Ghoneima, Yehea Ismail, Muhammad M Khellah, J TschanzAbstract:As technology scales, the shrinking wire Width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of Bus lines of the conventional parallel-line Bus CB architecture by multiplexing each m-bits onto a single line. This Bus architecture, the serial-link Bus SLB, transforms an n-bit conventional parallel-line Bus into an n/m-line (serial-link) Bus. The advantage of serial-link Buses is that they have fewer lines, and if the Bus Width is kept the same, serial- link Buses will have larger line Width and spacing. Increasing the line Width has a twofold reduction effect on the line resistance, as the resistivity of sub-100 nm wires significantly drops as the line Width increases. Also, increasing the line Width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m exists that minimizes the Bus energy dissipation and maximizes the Bus throughput per-unit area. The optimum degree of multiplexing for maximum throughput-per- unit-area and for minimum energy dissipation for the 25-130 nm technologies was determined in this paper. HSPICE simulations show that; for the same throughput-per-unit-area as conventional parallel-line Buses, the serial-link Bus architecture reduces the energy dissipation by up to 31.42% for a 64-bit Bus implemented in an intermediate metal layer of a 50 nm technology and a reduction of 52.7% is projected for the 25 nm technology.
Kaustav Banerjee - One of the best experts on this subject based on the ideXlab platform.
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a thermally aware performance analysis of vertically integrated 3 d processor memory hierarchy
Design Automation Conference, 2006Co-Authors: Gian Luca Loi, Banit Agrawal, Navin Srivastava, Shengchih Lin, Timothy Sherwood, Kaustav BanerjeeAbstract:Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several other advantages, it is expected that the benefits from this technology can potentially be off-set by thermal considerations which impact chip performance and reliability. The work presented in this paper is the first attempt to study the performance benefits of 3-D technology under the influence of such thermal constraints. Using a processor-cache-memory system and carefully chosen applications encompassing different memory behaviors, the performance of 3-D architecture is compared with a conventional planar (2-D) design. It is found that the substantial increase in memory Bus frequency and Bus Width contribute to a significant reduction in execution time with a 3-D design. It is also found that increasing the clock frequency translates into larger gains in system performance with 3-D designs than for planar 2-D designs in memory intensive applications. The thermal profile of the vertically stacked chip is generated taking into account the highly temperature sensitive leakage power dissipation. The maximum allowed operating frequency imposed by temperature constraint is shown to be lower for 3-D than for 2-D designs. In spite of these constraints, it is shown that the 3-D system registers large performance improvement for memory intensive applications.
A Hlawiczka - One of the best experts on this subject based on the ideXlab platform.
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testing of interconnections with use of reduced size signature based diagnostic dictionary
Elektronika : konstrukcje technologie zastosowania, 2010Co-Authors: T Garbolino, K Gucwa, A HlawiczkaAbstract:The paper presents a new method for size reduction of a signature-based diagnostic dictionary that is normally used for testing of static and delay faults in interconnections that are tested by means of an R-LFSR ring register. The newly developed method, similarly to the previous studies of the authors, assume that the n-bit Bus under test is split into b fragments with their Width of k bits each. Next, each fragment of the Bus is tested with use of a separate 2k-bit R-LFSR. This paper, suggests subdivision of the test procedure into four phases and alternate operation of odd and even registers. Such an approach eliminates effect of mutual impact between states of neighbouring R-LFSR's in case of shorts between feedback lines of these registers. These possible interactions were a drawback of previous solutions as they limited the possibility to reduce size of the diagnostic dictionary. Owing to application of this new technique to full detection, localization and identification of all the considered faults that may occur on an n-bit Bus, the new solution needs much smaller dictionary, where its size is determined by the multiplicity r of faults within each k-bit fragment, even if the Bus Width n≫k.
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reduced size signature based diagnostic dictionary for interconnection testing
Programmable Devices and Embedded Systems, 2010Co-Authors: T Garbolino, K Gucwa, A HlawiczkaAbstract:Abstract The paper deals with a new and advanced method intended to reduce size of a diagnostic dictionary that is used for detection, localization and identification of static and delay faults in interconnections that are tested with use of ring linear feedback shift registers (R-LFSR). The proposed method assumes that the Bus under test comprises n lines and is structured into b fragments with the size of k lines per each fragment. The method also assumes that each of the aforementioned fragments is tested by means of a separate R-LFSR with its length of 2k bits. In addition, the paper proposes to subdivide the test procedure into four phases whereas odd and even R-LFSRs are activated alternately. It is the way of subdivision that makes it possible to get rid of the mutual interference between two adjacent R-LFSRs when a short between feedback lines of these neighbouring registers takes place. Likelihood of such interactions was the drawback of previous methods and presented the impediment that prevented the fault dictionary from having its size reduced. The innovative solution that is suggested in this study enables to substantially diminish the dictionary, where its actual size is determined by the multiplicity of r defects within each k -bit part of the connecting Bus, even when the Bus Width n >> k .
Yehea Ismail - One of the best experts on this subject based on the ideXlab platform.
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serial link Bus a low power on chip Bus architecture
IEEE Transactions on Circuits and Systems, 2009Co-Authors: Maged Ghoneima, Yehea Ismail, Muhammad M Khellah, J TschanzAbstract:As technology scales, the shrinking wire Width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of Bus lines of the conventional parallel-line Bus (PLB) architecture by multiplexing each m-bits onto a single line. This Bus architecture, the serial-link Bus (SLB), transforms an n-bit conventional PLB into an n/m-line (serial link) Bus. The advantage of SLBs is that they have fewer lines, and if the Bus Width is kept the same, SLBs will have a larger line pitch. Increasing the line Width has a twofold reduction effect on the line resistance; as the resistivity of sub-100 nm wires drops significantly, the line Width increases. Also, increasing the line Width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m opt and an optimum Width to pitch ratio etaopt exist, which minimizes the Bus energy dissipation and maximizes the Bus throughput per unit area. The optimum degree of multiplexing and optimum Width-to-pitch ratio for maximum throughput per unit area and minimum energy dissipation for the 25-130-nm technologies was determined in this paper. Also, an encoding technique was proposed and implemented to reduce the switch activity penalty due to serialization. HSPICE simulations show that for the same throughput per unit area as conventional parallel-line data Buses, the SLB architecture reduces the energy dissipation by up to 31% for a 64-bit Bus implemented in an intermediate metal layer of a 50-nm technology, and a reduction of 53% is projected for a 25-nm technology.
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serial link Bus a low power on chip Bus architecture
International Conference on Computer Aided Design, 2005Co-Authors: Maged Ghoneima, Yehea Ismail, Muhammad M Khellah, J TschanzAbstract:As technology scales, the shrinking wire Width increases the interconnect resistivity, while the decreasing interconnect spacing significantly increases the coupling capacitance. This paper proposes reducing the number of Bus lines of the conventional parallel-line Bus CB architecture by multiplexing each m-bits onto a single line. This Bus architecture, the serial-link Bus SLB, transforms an n-bit conventional parallel-line Bus into an n/m-line (serial-link) Bus. The advantage of serial-link Buses is that they have fewer lines, and if the Bus Width is kept the same, serial- link Buses will have larger line Width and spacing. Increasing the line Width has a twofold reduction effect on the line resistance, as the resistivity of sub-100 nm wires significantly drops as the line Width increases. Also, increasing the line Width and spacing reduces the coupling capacitance between adjacent lines, but increases the line-to-ground capacitance. Thus, an optimum degree of multiplexing m exists that minimizes the Bus energy dissipation and maximizes the Bus throughput per-unit area. The optimum degree of multiplexing for maximum throughput-per- unit-area and for minimum energy dissipation for the 25-130 nm technologies was determined in this paper. HSPICE simulations show that; for the same throughput-per-unit-area as conventional parallel-line Buses, the serial-link Bus architecture reduces the energy dissipation by up to 31.42% for a 64-bit Bus implemented in an intermediate metal layer of a 50 nm technology and a reduction of 52.7% is projected for the 25 nm technology.
