The Experts below are selected from a list of 1791 Experts worldwide ranked by ideXlab platform

Ken Kennedy - One of the best experts on this subject based on the ideXlab platform.

  • International Journal of High Performance Systems Architecture, Vol. x, No. x, xxxx 1 Model-guided Empirical Tuning of Loop Fusion
    2015
    Co-Authors: Apan Qasem, Ken Kennedy
    Abstract:

    Abstract: Loop fusion is recognized as an effective transformation for improving memory hierarchy performance. However, unconstrained loop fusion can lead to poor performance because of increased register pressure and Cache Conflict misses. In this paper, we present a Cache-conscious analytical model for profitable loop fusion. We use this model to tune fusion parameters for different architectures through empirical search. Experiments on four different platforms for a set of applications show significant speedup over fully optimized code generated by state-of-the-art commercial compilers

  • a Cache conscious profitability model for empirical tuning of loop fusion
    Lecture Notes in Computer Science, 2006
    Co-Authors: Apan Qasem, Ken Kennedy
    Abstract:

    Loop fusion is recognized as an effective program transformation for improving memory hierarchy performance. However, unconstrained loop fusion can lead to poor performance because of increased register pressure and Cache Conflict misses. The complex interaction between different levels of the memory hierarchy with the input program makes it very difficult to always make the right choice in fusing loops. In this paper, we present a Cache-conscious analytical model for profitable loop fusion to be used with a constrained weighted fusion algorithm. We then extend the model to show its effectiveness in the context of an empirical tuning framework. A preliminary evaluation of the model is presented using hand experiments on four applications.

Nigel Topham - One of the best experts on this subject based on the ideXlab platform.

  • Eliminating Cache Conflict Misses Through XOR-Based Placement Functions
    2008
    Co-Authors: Antonio Gonzalez, Mateo Valero, Nigel Topham, Joan M. Parcerisa
    Abstract:

    This paper makes the case for the use of XOR-based placement functions for Cache memories. It shows that these XOR-mapping schemes can eliminate many Conflict misses for direct-mapped and victim Caches and practically all of them for (pseudo) two-way associative organizations. The paper evaluates the performance of XOR-mapping schemes for a number of different Cache organizations: direct-mapped, set-associative, victim, hash-rehash, column-associative and skewed-associative. It also proposes novel replacement policies for some of these Cache organizations. In particular, it presents a low-cost implementation of a LRU replacement policy which demonstrates a significant improvement over the pseudo-LRU replacement previously proposed. The paper shows that for a 8 Kbyte data Cache, XOR-mapping schemes approximately halve the miss ratio for two-way associative and column-associative organizations. Skewed-associative Caches, which already make use of XOR-mapping functions, can benefit from the LRU replacement and also from the use of more sophisticated mapping functions. For two-way associative, columnassociative and two-way skewed-associative organizations, XORmapping schemes achieve a miss ratio that is not higher than 1.10 times that of a fully-associative Cache. XOR mapping schemes also provide a very significant reduction in the miss ratio for the other Cache organizations, including the direct-mapped Cache. Ultimately, the conclusion of this study is that XOR-based placement functions unequivocally provide highly significant performance benefits to most Cache organizations

  • the design and performance of a Conflict avoiding Cache
    International Symposium on Microarchitecture, 1997
    Co-Authors: Nigel Topham, Antonio Gonzalez, Jose Gabriel Ruiz Gonzalez
    Abstract:

    High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for Cache Conflict-avoidance schemes. We investigate the design and performance of Conflict-avoiding Cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing Conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed Caches are both effective in performance terms and practical from an implementation viewpoint.

  • eliminating Cache Conflict misses through xor based placement functions
    International Conference on Supercomputing, 1997
    Co-Authors: Antonio Gonzalez, Mateo Valero, Nigel Topham, Joan M. Parcerisa
    Abstract:

    This paper makes the case for the use of XOR-based placement functions for Cache memories. It shows that these XOR-mapping schemes can eliminate many Conflict misses for direct-mapped and victim Caches and practically all of them for (pseudo) two-way associative organizations. The paper evaluates the performance of XOR-mapping schemes for a number of different Cache organizations: direct-mapped, set-associative, victim, hash-rehash, column-associative and skewed-associative. It also proposes novel replacement policies for some of these Cache organizations. In particular, it presents a low-cost implementation of a pure LRU replacement policy which demonstrates a significant improvement over the pseudo-LRU replacement previously proposed. The paper shows that for a 8 Kbyte data Cache, XOR-mapping schemes approximately halve the miss ratio for two-way associative and column-associative organizations. Skewed-associative Caches, which already make use of XOR-mapping functions, can benefit from the LRU replacement and also from the use of more sophisticated mapping functions. For two-way associative, columnassociative and two-way skewed-associative organizations, XORmapping schemes achieve a miss ratio that is not higher than 1.10 times that of a fully-associative Cache. XOR mapping schemes also provide a very significant reduction in the miss ratio for the other Cache organizations, including the direct-mapped Cache. Ultimately, the conclusion of this study is that XOR-based placement functions unequivocally provide highly significant performance benefits to most Cache organizations.

Antonio Gonzalez - One of the best experts on this subject based on the ideXlab platform.

  • Eliminating Cache Conflict Misses Through XOR-Based Placement Functions
    2008
    Co-Authors: Antonio Gonzalez, Mateo Valero, Nigel Topham, Joan M. Parcerisa
    Abstract:

    This paper makes the case for the use of XOR-based placement functions for Cache memories. It shows that these XOR-mapping schemes can eliminate many Conflict misses for direct-mapped and victim Caches and practically all of them for (pseudo) two-way associative organizations. The paper evaluates the performance of XOR-mapping schemes for a number of different Cache organizations: direct-mapped, set-associative, victim, hash-rehash, column-associative and skewed-associative. It also proposes novel replacement policies for some of these Cache organizations. In particular, it presents a low-cost implementation of a LRU replacement policy which demonstrates a significant improvement over the pseudo-LRU replacement previously proposed. The paper shows that for a 8 Kbyte data Cache, XOR-mapping schemes approximately halve the miss ratio for two-way associative and column-associative organizations. Skewed-associative Caches, which already make use of XOR-mapping functions, can benefit from the LRU replacement and also from the use of more sophisticated mapping functions. For two-way associative, columnassociative and two-way skewed-associative organizations, XORmapping schemes achieve a miss ratio that is not higher than 1.10 times that of a fully-associative Cache. XOR mapping schemes also provide a very significant reduction in the miss ratio for the other Cache organizations, including the direct-mapped Cache. Ultimately, the conclusion of this study is that XOR-based placement functions unequivocally provide highly significant performance benefits to most Cache organizations

  • the design and performance of a Conflict avoiding Cache
    International Symposium on Microarchitecture, 1997
    Co-Authors: Nigel Topham, Antonio Gonzalez, Jose Gabriel Ruiz Gonzalez
    Abstract:

    High performance architectures depend heavily on efficient multi-level memory hierarchies to minimize the cost of accessing data. This dependence will increase with the expected increases in relative distance to main memory. There have been a number of published proposals for Cache Conflict-avoidance schemes. We investigate the design and performance of Conflict-avoiding Cache architectures based on polynomial modulus functions, which earlier research has shown to be highly effective at reducing Conflict miss ratios. We examine a number of practical implementation issues and present experimental evidence to support the claim that pseudo-randomly indexed Caches are both effective in performance terms and practical from an implementation viewpoint.

  • eliminating Cache Conflict misses through xor based placement functions
    International Conference on Supercomputing, 1997
    Co-Authors: Antonio Gonzalez, Mateo Valero, Nigel Topham, Joan M. Parcerisa
    Abstract:

    This paper makes the case for the use of XOR-based placement functions for Cache memories. It shows that these XOR-mapping schemes can eliminate many Conflict misses for direct-mapped and victim Caches and practically all of them for (pseudo) two-way associative organizations. The paper evaluates the performance of XOR-mapping schemes for a number of different Cache organizations: direct-mapped, set-associative, victim, hash-rehash, column-associative and skewed-associative. It also proposes novel replacement policies for some of these Cache organizations. In particular, it presents a low-cost implementation of a pure LRU replacement policy which demonstrates a significant improvement over the pseudo-LRU replacement previously proposed. The paper shows that for a 8 Kbyte data Cache, XOR-mapping schemes approximately halve the miss ratio for two-way associative and column-associative organizations. Skewed-associative Caches, which already make use of XOR-mapping functions, can benefit from the LRU replacement and also from the use of more sophisticated mapping functions. For two-way associative, columnassociative and two-way skewed-associative organizations, XORmapping schemes achieve a miss ratio that is not higher than 1.10 times that of a fully-associative Cache. XOR mapping schemes also provide a very significant reduction in the miss ratio for the other Cache organizations, including the direct-mapped Cache. Ultimately, the conclusion of this study is that XOR-based placement functions unequivocally provide highly significant performance benefits to most Cache organizations.

Alex Orailoglu - One of the best experts on this subject based on the ideXlab platform.

  • branch prediction directed dynamic instruction Cache locking for embedded systems
    ACM Transactions in Embedded Computing Systems, 2014
    Co-Authors: Keni Qiu, Mengying Zhao, Chun Jason Xue, Alex Orailoglu
    Abstract:

    Cache locking is a Cache management technique to preclude the replacement of locked Cache contents. Cache locking is often adopted to improve Cache access predictability in Worst-Case Execution Time (WCET) analysis. Static Cache locking methods have been proposed recently to improve Average-Case Execution Time (ACET) performance. This article presents an approach, Branch Prediction-directed Dynamic Cache Locking (BPDCL), to improve system performance through Cache Conflict miss reduction. In the proposed approach, the control flow graph of a program is first partitioned into disjoint execution regions, then memory blocks worth locking are determined by calculating the locking profit for each region. These two steps are conducted during compilation time. At runtime, directed by branch predictions, locking routines are prefetched into a small high-speed buffer. The predetermined Cache locking contents are loaded and locked at specific execution points during program execution. Experimental results show that the proposed BPDCL method exhibits an average improvement of 25.9p, 13.8p, and 8.0p on Cache miss rate reduction in comparison to cases with no Cache locking, the static locking method, and the dynamic locking method, respectively.

  • branch prediction directed dynamic instruction Cache locking for embedded systems
    Embedded and Real-Time Computing Systems and Applications, 2013
    Co-Authors: Keni Qiu, Mengying Zhao, Chun Jason Xue, Alex Orailoglu
    Abstract:

    Cache locking is a Cache management technique to preclude the replacement of locked Cache contents. Cache locking is often used to improve Cache access predictability in Worst-Case Execution Time (WCET) analysis. Static Cache locking methods have been proposed recently to improve average system performance. This paper presents an approach, Branch Prediction directed Dynamic Cache Locking (BPDCL), to improve average system performance through effective Cache Conflict miss reduction in different execution regions. In this proposed approach, the control flow graph of a program is partitioned into regions and memory blocks worth locking for each region are calculated during compilation time. At runtime, directed by branch predictions, locking routines are prefetched into a high-speed buffer. The pre-determined Cache locking contents are loaded and locked at specific execution points during program execution. Experimental results show that the proposed BPDCL method exhibits an average improvement of 21.8% and 10.3% on Cache miss rate reduction in comparison to the case with no Cache locking and the static locking method respectively.

Apan Qasem - One of the best experts on this subject based on the ideXlab platform.

  • International Journal of High Performance Systems Architecture, Vol. x, No. x, xxxx 1 Model-guided Empirical Tuning of Loop Fusion
    2015
    Co-Authors: Apan Qasem, Ken Kennedy
    Abstract:

    Abstract: Loop fusion is recognized as an effective transformation for improving memory hierarchy performance. However, unconstrained loop fusion can lead to poor performance because of increased register pressure and Cache Conflict misses. In this paper, we present a Cache-conscious analytical model for profitable loop fusion. We use this model to tune fusion parameters for different architectures through empirical search. Experiments on four different platforms for a set of applications show significant speedup over fully optimized code generated by state-of-the-art commercial compilers

  • a Cache conscious profitability model for empirical tuning of loop fusion
    Lecture Notes in Computer Science, 2006
    Co-Authors: Apan Qasem, Ken Kennedy
    Abstract:

    Loop fusion is recognized as an effective program transformation for improving memory hierarchy performance. However, unconstrained loop fusion can lead to poor performance because of increased register pressure and Cache Conflict misses. The complex interaction between different levels of the memory hierarchy with the input program makes it very difficult to always make the right choice in fusing loops. In this paper, we present a Cache-conscious analytical model for profitable loop fusion to be used with a constrained weighted fusion algorithm. We then extend the model to show its effectiveness in the context of an empirical tuning framework. A preliminary evaluation of the model is presented using hand experiments on four applications.