The Experts below are selected from a list of 8886 Experts worldwide ranked by ideXlab platform
Ahmet T Erdogan - One of the best experts on this subject based on the ideXlab platform.
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ISVLSI - Enhanced dual strategy based VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006Co-Authors: Zahid Khan, Tughrul Arslan, John Thompson, Ahmet T ErdoganAbstract:Multiple input multiple output (MIMO) wireless technology involves highly complex signal processing which is directly related to increased power and area consumption in VLSI architecture. This paper proposes an enhanced dual strategy based VLSI architecture developed for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. The architecture concurrently addresses algorithmic optimization of number of multipliers while at the same time allowing for intelligent selective clock gating to disable the clock to those portions of the architecture that remain inactive during period of computation. Results indicate overall 36% power and 31% area reduction compared to previous architecture without degrading the BER performance.
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VLSI Design - Area & power efficient VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006Co-Authors: Zahid Khan, Tughrul Arslan, John Thompson, Ahmet T ErdoganAbstract:Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and power consumption of electronic systems. The situation becomes even worse if wireless systems are equipped with multiple input and multiple output (MIMO) technology which involves highly complex signal processing. This paper proposes an area and power efficient VLSI architecture for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. Results indicate 25% area and 24% power reduction compared to previous architecture in the literature without degrading the BER performance.
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Enhanced dual strategy based VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, 2006Co-Authors: Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T ErdoganAbstract:Multiple input multiple output (MIMO) wireless technology involves highly complex signal processing which is directly related to increased power and area consumption in VLSI architecture. This paper proposes an enhanced dual strategy based VLSI architecture developed for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. The architecture concurrently addresses algorithmic optimization of number of multipliers while at the same time allowing for intelligent selective clock gating to disable the clock to those portions of the architecture that remain inactive during period of computation. Results indicate overall 36% power and 31% area reduction compared to previous architecture without degrading the BER performance.
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area power efficient vlsi architecture for computing pseudo inverse of Channel Matrix in a mimo wireless system
International Conference on VLSI Design, 2006Co-Authors: Zahid Khan, Tughrul Arslan, John Thompson, Ahmet T ErdoganAbstract:Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and power consumption of electronic systems. The situation becomes even worse if wireless systems are equipped with multiple input and multiple output (MIMO) technology which involves highly complex signal processing. This paper proposes an area and power efficient VLSI architecture for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. Results indicate 25% area and 24% power reduction compared to previous architecture in the literature without degrading the BER performance.
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Area & power efficient VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006Co-Authors: Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T ErdoganAbstract:Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and power consumption of electronic systems. The situation becomes even worse if wireless systems are equipped with multiple input and multiple output (MIMO) technology which involves highly complex signal processing. This paper proposes an area and power efficient VLSI architecture for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. Results indicate 25% area and 24% power reduction compared to previous architecture in the literature without degrading the BER performance.
Zahid Khan - One of the best experts on this subject based on the ideXlab platform.
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ISVLSI - Enhanced dual strategy based VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006Co-Authors: Zahid Khan, Tughrul Arslan, John Thompson, Ahmet T ErdoganAbstract:Multiple input multiple output (MIMO) wireless technology involves highly complex signal processing which is directly related to increased power and area consumption in VLSI architecture. This paper proposes an enhanced dual strategy based VLSI architecture developed for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. The architecture concurrently addresses algorithmic optimization of number of multipliers while at the same time allowing for intelligent selective clock gating to disable the clock to those portions of the architecture that remain inactive during period of computation. Results indicate overall 36% power and 31% area reduction compared to previous architecture without degrading the BER performance.
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VLSI Design - Area & power efficient VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006Co-Authors: Zahid Khan, Tughrul Arslan, John Thompson, Ahmet T ErdoganAbstract:Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and power consumption of electronic systems. The situation becomes even worse if wireless systems are equipped with multiple input and multiple output (MIMO) technology which involves highly complex signal processing. This paper proposes an area and power efficient VLSI architecture for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. Results indicate 25% area and 24% power reduction compared to previous architecture in the literature without degrading the BER performance.
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Enhanced dual strategy based VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, 2006Co-Authors: Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T ErdoganAbstract:Multiple input multiple output (MIMO) wireless technology involves highly complex signal processing which is directly related to increased power and area consumption in VLSI architecture. This paper proposes an enhanced dual strategy based VLSI architecture developed for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. The architecture concurrently addresses algorithmic optimization of number of multipliers while at the same time allowing for intelligent selective clock gating to disable the clock to those portions of the architecture that remain inactive during period of computation. Results indicate overall 36% power and 31% area reduction compared to previous architecture without degrading the BER performance.
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area power efficient vlsi architecture for computing pseudo inverse of Channel Matrix in a mimo wireless system
International Conference on VLSI Design, 2006Co-Authors: Zahid Khan, Tughrul Arslan, John Thompson, Ahmet T ErdoganAbstract:Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and power consumption of electronic systems. The situation becomes even worse if wireless systems are equipped with multiple input and multiple output (MIMO) technology which involves highly complex signal processing. This paper proposes an area and power efficient VLSI architecture for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. Results indicate 25% area and 24% power reduction compared to previous architecture in the literature without degrading the BER performance.
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Area & power efficient VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006Co-Authors: Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T ErdoganAbstract:Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and power consumption of electronic systems. The situation becomes even worse if wireless systems are equipped with multiple input and multiple output (MIMO) technology which involves highly complex signal processing. This paper proposes an area and power efficient VLSI architecture for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. Results indicate 25% area and 24% power reduction compared to previous architecture in the literature without degrading the BER performance.
J. Chambers - One of the best experts on this subject based on the ideXlab platform.
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Spatial-temporal mode transmission based upon the QR decomposition of a polynomial Channel Matrix with uncertainties
2010 18th European Signal Processing Conference, 2010Co-Authors: J. Foster, J. Mcwhirter, M. Davies, S. Lambotharan, J. ChambersAbstract:This paper presents an entirely time domain approach for communicating over frequency selective multiple-input multiple-output (MIMO) Channels. The proposed system applies a paraunitary Matrix to the received signals, which is specifically designed to transform the effective polynomial Channel Matrix for the system into an upper triangular polynomial Matrix. This then enables the MIMO Channel equalisation problem to be transformed into a set of single-input single-output (SISO) equalisation problems, by exploiting the upper triangular structure of the transformed Channel Matrix, which can then be individually solved using Turbo equalisation. In particular, this paper investigates how the system performs when there is error present in the Channel Matrix state information and discusses the possible errors that are encountered when formulating the QR decomposition (QRD) of a polynomial Matrix.
J. Foster - One of the best experts on this subject based on the ideXlab platform.
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EUSIPCO - Spatial-temporal mode transmission based upon the QR decomposition of a polynomial Channel Matrix with uncertainties
2020Co-Authors: J. Foster, J. Mcwhirter, M. Davies, S. Lambotharan, Jonathon A. ChambersAbstract:This paper presents an entirely time domain approach for communicating over frequency selective multiple-input multiple-output (MIMO) Channels. The proposed system applies a paraunitary Matrix to the received signals, which is specifically designed to transform the effective polynomial Channel Matrix for the system into an upper triangular polynomial Matrix. This then enables the MIMO Channel equalisation problem to be transformed into a set of single-input single-output (SISO) equalisation problems, by exploiting the upper triangular structure of the transformed Channel Matrix, which can then be individually solved using Turbo equalisation. In particular, this paper investigates how the system performs when there is error present in the Channel Matrix state information and discusses the possible errors that are encountered when formulating the QR decomposition (QRD) of a polynomial Matrix.
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Spatial-temporal mode transmission based upon the QR decomposition of a polynomial Channel Matrix with uncertainties
2010 18th European Signal Processing Conference, 2010Co-Authors: J. Foster, J. Mcwhirter, M. Davies, S. Lambotharan, J. ChambersAbstract:This paper presents an entirely time domain approach for communicating over frequency selective multiple-input multiple-output (MIMO) Channels. The proposed system applies a paraunitary Matrix to the received signals, which is specifically designed to transform the effective polynomial Channel Matrix for the system into an upper triangular polynomial Matrix. This then enables the MIMO Channel equalisation problem to be transformed into a set of single-input single-output (SISO) equalisation problems, by exploiting the upper triangular structure of the transformed Channel Matrix, which can then be individually solved using Turbo equalisation. In particular, this paper investigates how the system performs when there is error present in the Channel Matrix state information and discusses the possible errors that are encountered when formulating the QR decomposition (QRD) of a polynomial Matrix.
Tughrul Arslan - One of the best experts on this subject based on the ideXlab platform.
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ISVLSI - Enhanced dual strategy based VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06), 2006Co-Authors: Zahid Khan, Tughrul Arslan, John Thompson, Ahmet T ErdoganAbstract:Multiple input multiple output (MIMO) wireless technology involves highly complex signal processing which is directly related to increased power and area consumption in VLSI architecture. This paper proposes an enhanced dual strategy based VLSI architecture developed for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. The architecture concurrently addresses algorithmic optimization of number of multipliers while at the same time allowing for intelligent selective clock gating to disable the clock to those portions of the architecture that remain inactive during period of computation. Results indicate overall 36% power and 31% area reduction compared to previous architecture without degrading the BER performance.
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VLSI Design - Area & power efficient VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006Co-Authors: Zahid Khan, Tughrul Arslan, John Thompson, Ahmet T ErdoganAbstract:Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and power consumption of electronic systems. The situation becomes even worse if wireless systems are equipped with multiple input and multiple output (MIMO) technology which involves highly complex signal processing. This paper proposes an area and power efficient VLSI architecture for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. Results indicate 25% area and 24% power reduction compared to previous architecture in the literature without degrading the BER performance.
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Enhanced dual strategy based VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006, 2006Co-Authors: Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T ErdoganAbstract:Multiple input multiple output (MIMO) wireless technology involves highly complex signal processing which is directly related to increased power and area consumption in VLSI architecture. This paper proposes an enhanced dual strategy based VLSI architecture developed for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. The architecture concurrently addresses algorithmic optimization of number of multipliers while at the same time allowing for intelligent selective clock gating to disable the clock to those portions of the architecture that remain inactive during period of computation. Results indicate overall 36% power and 31% area reduction compared to previous architecture without degrading the BER performance.
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area power efficient vlsi architecture for computing pseudo inverse of Channel Matrix in a mimo wireless system
International Conference on VLSI Design, 2006Co-Authors: Zahid Khan, Tughrul Arslan, John Thompson, Ahmet T ErdoganAbstract:Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and power consumption of electronic systems. The situation becomes even worse if wireless systems are equipped with multiple input and multiple output (MIMO) technology which involves highly complex signal processing. This paper proposes an area and power efficient VLSI architecture for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. Results indicate 25% area and 24% power reduction compared to previous architecture in the literature without degrading the BER performance.
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Area & power efficient VLSI architecture for computing pseudo inverse of Channel Matrix in a MIMO wireless system
19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006Co-Authors: Zahid Khan, John S. Thompson, Tughrul Arslan, Ahmet T ErdoganAbstract:Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and power consumption of electronic systems. The situation becomes even worse if wireless systems are equipped with multiple input and multiple output (MIMO) technology which involves highly complex signal processing. This paper proposes an area and power efficient VLSI architecture for computing the pseudo inverse of augmented Channel Matrix used in MIMO systems. Results indicate 25% area and 24% power reduction compared to previous architecture in the literature without degrading the BER performance.