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Maurizio Gaibotti - One of the best experts on this subject based on the ideXlab platform.

  • Charge Pump Circuits: Power consumption optimization-a summary
    IEEE Circuits and Systems Magazine, 2004
    Co-Authors: Gaetano Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this paper, an optimized strategy for designing Charge Pumps with minimum power consumption is presented. The approach allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency. Capacitor value is then set to provide the current capability required. This approach was analytically developed and validated through simulations and experimental measurements on 0.35-μm EEPROM CMOS technology. This approach was then compared with one which minimized the silicon area and it was shown that only a small increase in area is needed to minimize power consumption.

  • Charge Pump Circuits power consumption optimization
    IEEE Transactions on Circuits and Systems I-regular Papers, 2002
    Co-Authors: G Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this paper, an optimized strategy for designing Charge Pumps with minimum power consumption is presented. The approach allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency. Capacitor value is then set to provide the current capability required. This approach was analytically developed and validated through simulations and experimental measurements on 0.35-/spl mu/m EEPROM CMOS technology. This approach was then compared with one which minimized the silicon area and it was shown that only a small increase in area is needed to minimize power consumption.

  • ISCAS (4) - Modeling and minimization of power consumption in Charge Pump Circuits
    ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001
    Co-Authors: G Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this communication, starting from a power consumption model, an optimized strategy to design Charge Pumps with the minimum power consumption is presented. The approach allows one to define the number of stages that for a given input and output voltage maximizes the power efficiency. Capacitor value is then set to provide the required current capability. The approach was analytically developed and was validated through simulations on 0.35 /spl mu/m EEPROM technology.

  • modeling and minimization of power consumption in Charge Pump Circuits
    International Symposium on Circuits and Systems, 2001
    Co-Authors: G Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this communication, starting from a power consumption model, an optimized strategy to design Charge Pumps with the minimum power consumption is presented. The approach allows one to define the number of stages that for a given input and output voltage maximizes the power efficiency. Capacitor value is then set to provide the required current capability. The approach was analytically developed and was validated through simulations on 0.35 /spl mu/m EEPROM technology.

Domenico Pappalardo - One of the best experts on this subject based on the ideXlab platform.

  • Charge Pump Circuits: An overview on design strategies and topologies
    IEEE Circuits and Systems Magazine, 2010
    Co-Authors: Gaetano Palumbo, Domenico Pappalardo
    Abstract:

    Due to the continuous power supply reduction, Charge Pumps Circuits are widely used in integrated Circuits (ICs) devoted to several kind of applications such as smart power, nonvolatile memories, switched capacitor Circuits, operational amplifiers, voltage regulators, SRAMs, LCD drivers, piezoelectric actuators, RF antenna switch controllers, etc. The main focus of this tutorial manuscript is to provide a deep understanding of the Charge Pumps behavior, to present useful models and key parameters and to organically and in details discuss the optimized design strategies. Finally, an overview of the main different topologies is also included.

  • Charge Pump Circuits: Power consumption optimization-a summary
    IEEE Circuits and Systems Magazine, 2004
    Co-Authors: Gaetano Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this paper, an optimized strategy for designing Charge Pumps with minimum power consumption is presented. The approach allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency. Capacitor value is then set to provide the current capability required. This approach was analytically developed and validated through simulations and experimental measurements on 0.35-μm EEPROM CMOS technology. This approach was then compared with one which minimized the silicon area and it was shown that only a small increase in area is needed to minimize power consumption.

  • Charge Pump Circuits power consumption optimization
    IEEE Transactions on Circuits and Systems I-regular Papers, 2002
    Co-Authors: G Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this paper, an optimized strategy for designing Charge Pumps with minimum power consumption is presented. The approach allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency. Capacitor value is then set to provide the current capability required. This approach was analytically developed and validated through simulations and experimental measurements on 0.35-/spl mu/m EEPROM CMOS technology. This approach was then compared with one which minimized the silicon area and it was shown that only a small increase in area is needed to minimize power consumption.

  • ISCAS (4) - Modeling and minimization of power consumption in Charge Pump Circuits
    ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001
    Co-Authors: G Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this communication, starting from a power consumption model, an optimized strategy to design Charge Pumps with the minimum power consumption is presented. The approach allows one to define the number of stages that for a given input and output voltage maximizes the power efficiency. Capacitor value is then set to provide the required current capability. The approach was analytically developed and was validated through simulations on 0.35 /spl mu/m EEPROM technology.

  • modeling and minimization of power consumption in Charge Pump Circuits
    International Symposium on Circuits and Systems, 2001
    Co-Authors: G Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this communication, starting from a power consumption model, an optimized strategy to design Charge Pumps with the minimum power consumption is presented. The approach allows one to define the number of stages that for a given input and output voltage maximizes the power efficiency. Capacitor value is then set to provide the required current capability. The approach was analytically developed and was validated through simulations on 0.35 /spl mu/m EEPROM technology.

Toru Tanzawa - One of the best experts on this subject based on the ideXlab platform.

  • An Optimum Design of Clocked AC-DC Charge Pump Circuits for Vibration Energy Harvesting
    Electronics, 2020
    Co-Authors: Toru Tanzawa
    Abstract:

    This paper shows how clocked AC-DC Charge Pump Circuits can be optimally designed to have the minimum circuit area for small form factor vibration energy harvesting. One can determine an optimum number of stages with simple equations and then determine the capacitance of each Pump capacitor to have a target output current at a target output voltage. The equations were verified under a wide range of design parameters by comparing the output current with the simulated one. The output current of the circuit designed by the equations was in good agreement with the simulated result, to within 5% for 98% of the 1600 designs with different parameters. We also propose a design flow to help designers determine the initial design parameters of a clocked AC-DC Charge Pump circuit (i.e., the number of stages, capacitance per stage, and the total size of rectifying devices) under the condition that the saturation current of a unit of the rectifying device, clock frequency, amplitude of the voltage generated by the energy transducer, target output voltage, and target output current are given. SPICE simulation results validated theoretical results with an error of 3% in terms of the output current when a clocked AC-DC Charge Pump was designed to output current of 1 μA at 2.5 V from a vibration energy harvester with an AC voltage amplitude of 0.5 V.

  • toward a minimum operating voltage design of dc dc Charge Pump Circuits for energy harvesting
    International Symposium on Circuits and Systems, 2019
    Co-Authors: Shugo Tokuda, Toru Tanzawa
    Abstract:

    This paper expands upon the circuit model of DC-DC Charge Pump Circuits to include the reverse leakage current which becomes significant at extremely low voltages in energy harvesting. The paper proposes a design flow to determine all the design parameters of Charge Pump Circuits operating in sub-threshold region such as a clock frequency, stage capacitor size, rectifying device size and number of stages based on the model. The methodology is demonstrated and verified by SPICE simulation. By using the proposed flow under given conditions, circuit designers can numerically obtain trade-offs between power supply voltage, circuit area and power efficiency of DC-DC Charge Pump Circuits to design energy harvesting systems

  • ISCAS - Toward a Minimum-Operating-Voltage Design of DC-DC Charge Pump Circuits for Energy Harvesting
    2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019
    Co-Authors: Shugo Tokuda, Toru Tanzawa
    Abstract:

    This paper expands upon the circuit model of DC-DC Charge Pump Circuits to include the reverse leakage current which becomes significant at extremely low voltages in energy harvesting. The paper proposes a design flow to determine all the design parameters of Charge Pump Circuits operating in sub-threshold region such as a clock frequency, stage capacitor size, rectifying device size and number of stages based on the model. The methodology is demonstrated and verified by SPICE simulation. By using the proposed flow under given conditions, circuit designers can numerically obtain trade-offs between power supply voltage, circuit area and power efficiency of DC-DC Charge Pump Circuits to design energy harvesting systems

  • on the output impedance and an output current power efficiency relationship of dickson Charge Pump Circuits
    IEEE Transactions on Circuits and Systems Ii-express Briefs, 2018
    Co-Authors: Toru Tanzawa
    Abstract:

    This brief shows that the output impedance of Dickson Charge Pumps with an arbitrary number of stages defined by the total power loss in the switching devices and the output voltage is identical to the previous result calculated by the output current and voltage. A relationship between the output current and power efficiency is also given in a simple form.

  • A Behavior Model of a Dickson Charge Pump Circuit for Designing a Multiple Charge Pump System Distributed in LSIs
    IEEE Transactions on Circuits and Systems II: Express Briefs, 2010
    Co-Authors: Toru Tanzawa
    Abstract:

    This brief discusses how each of multiple Charge Pump Circuits in LSIs is designed in case where the power and ground line resistance is not negligible. A behavior model for a Charge Pump, including the local power and ground voltages as input parameters, is proposed and a systematic design methodology is then presented. A system designer can use the behavior model to determine the specifications on each Pump and power and ground resistance for minimizing overall area.

Gaetano Palumbo - One of the best experts on this subject based on the ideXlab platform.

  • Charge Pump Circuits: An overview on design strategies and topologies
    IEEE Circuits and Systems Magazine, 2010
    Co-Authors: Gaetano Palumbo, Domenico Pappalardo
    Abstract:

    Due to the continuous power supply reduction, Charge Pumps Circuits are widely used in integrated Circuits (ICs) devoted to several kind of applications such as smart power, nonvolatile memories, switched capacitor Circuits, operational amplifiers, voltage regulators, SRAMs, LCD drivers, piezoelectric actuators, RF antenna switch controllers, etc. The main focus of this tutorial manuscript is to provide a deep understanding of the Charge Pumps behavior, to present useful models and key parameters and to organically and in details discuss the optimized design strategies. Finally, an overview of the main different topologies is also included.

  • Charge Pump Circuits: Power consumption optimization-a summary
    IEEE Circuits and Systems Magazine, 2004
    Co-Authors: Gaetano Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this paper, an optimized strategy for designing Charge Pumps with minimum power consumption is presented. The approach allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency. Capacitor value is then set to provide the current capability required. This approach was analytically developed and validated through simulations and experimental measurements on 0.35-μm EEPROM CMOS technology. This approach was then compared with one which minimized the silicon area and it was shown that only a small increase in area is needed to minimize power consumption.

G Palumbo - One of the best experts on this subject based on the ideXlab platform.

  • Charge Pump Circuits with only capacitive loads: optimized design
    IEEE Transactions on Circuits and Systems Ii-express Briefs, 2006
    Co-Authors: G Palumbo, D. Pappalardo
    Abstract:

    Optimized strategies for designing Charge Pumps having only capacitive loads are presented. The design strategies developed are with minimum silicon area, which is equivalent to that with minimum rise time, and with minimum power consumption. The approach allows designers to define the number of stages that minimize silicon area (and minimize rise time) or maximize power efficiency for a given input and output voltage. The approaches were analytically developed and validated through simulations and experimental measurements on 0.18-/spl mu/m EEPROM CMOS technology. Moreover, a detail comparison between the two design strategies is also carried out.

  • Charge Pump Circuits power consumption optimization
    IEEE Transactions on Circuits and Systems I-regular Papers, 2002
    Co-Authors: G Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this paper, an optimized strategy for designing Charge Pumps with minimum power consumption is presented. The approach allows designers to define the number of stages that, for a given input, and an output voltage, maximize power efficiency. Capacitor value is then set to provide the current capability required. This approach was analytically developed and validated through simulations and experimental measurements on 0.35-/spl mu/m EEPROM CMOS technology. This approach was then compared with one which minimized the silicon area and it was shown that only a small increase in area is needed to minimize power consumption.

  • ISCAS (4) - Modeling and minimization of power consumption in Charge Pump Circuits
    ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2001
    Co-Authors: G Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this communication, starting from a power consumption model, an optimized strategy to design Charge Pumps with the minimum power consumption is presented. The approach allows one to define the number of stages that for a given input and output voltage maximizes the power efficiency. Capacitor value is then set to provide the required current capability. The approach was analytically developed and was validated through simulations on 0.35 /spl mu/m EEPROM technology.

  • modeling and minimization of power consumption in Charge Pump Circuits
    International Symposium on Circuits and Systems, 2001
    Co-Authors: G Palumbo, Domenico Pappalardo, Maurizio Gaibotti
    Abstract:

    In this communication, starting from a power consumption model, an optimized strategy to design Charge Pumps with the minimum power consumption is presented. The approach allows one to define the number of stages that for a given input and output voltage maximizes the power efficiency. Capacitor value is then set to provide the required current capability. The approach was analytically developed and was validated through simulations on 0.35 /spl mu/m EEPROM technology.