The Experts below are selected from a list of 184239 Experts worldwide ranked by ideXlab platform
Hyeonwoo Noh - One of the best experts on this subject based on the ideXlab platform.
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decoupled deep neural Network for semi supervised semantic segmentation
Neural Information Processing Systems, 2015Co-Authors: Seunghoo Hong, Hyeonwoo NohAbstract:We propose a novel deep neural Network architecture for semi-supervised semantic segmentation using heterogeneous annotations. Contrary to existing approaches posing semantic segmentation as a single task of region-based Classification, our algorithm decouples Classification and segmentation, and learns a separate Network for each task. In this architecture, labels associated with an image are identified by Classification Network, and binary segmentation is subsequently performed for each identified label in segmentation Network. The decoupled architecture enables us to learn Classification and segmentation Networks separately based on the training data with image-level and pixel-wise class labels, respectively. It facilitates to reduce search space for segmentation effectively by exploiting class-specific activation maps obtained from bridging layers. Our algorithm shows outstanding performance compared to other semi-supervised approaches with much less training images with strong annotations in PASCAL VOC dataset.
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decoupled deep neural Network for semi supervised semantic segmentation
arXiv: Computer Vision and Pattern Recognition, 2015Co-Authors: Seunghoon Hong, Hyeonwoo Noh, Bohyung HanAbstract:We propose a novel deep neural Network architecture for semi-supervised semantic segmentation using heterogeneous annotations. Contrary to existing approaches posing semantic segmentation as a single task of region-based Classification, our algorithm decouples Classification and segmentation, and learns a separate Network for each task. In this architecture, labels associated with an image are identified by Classification Network, and binary segmentation is subsequently performed for each identified label in segmentation Network. The decoupled architecture enables us to learn Classification and segmentation Networks separately based on the training data with image-level and pixel-wise class labels, respectively. It facilitates to reduce search space for segmentation effectively by exploiting class-specific activation maps obtained from bridging layers. Our algorithm shows outstanding performance compared to other semi-supervised approaches even with much less training images with strong annotations in PASCAL VOC dataset.
Seunghoo Hong - One of the best experts on this subject based on the ideXlab platform.
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decoupled deep neural Network for semi supervised semantic segmentation
Neural Information Processing Systems, 2015Co-Authors: Seunghoo Hong, Hyeonwoo NohAbstract:We propose a novel deep neural Network architecture for semi-supervised semantic segmentation using heterogeneous annotations. Contrary to existing approaches posing semantic segmentation as a single task of region-based Classification, our algorithm decouples Classification and segmentation, and learns a separate Network for each task. In this architecture, labels associated with an image are identified by Classification Network, and binary segmentation is subsequently performed for each identified label in segmentation Network. The decoupled architecture enables us to learn Classification and segmentation Networks separately based on the training data with image-level and pixel-wise class labels, respectively. It facilitates to reduce search space for segmentation effectively by exploiting class-specific activation maps obtained from bridging layers. Our algorithm shows outstanding performance compared to other semi-supervised approaches with much less training images with strong annotations in PASCAL VOC dataset.
Yizhuang Xie - One of the best experts on this subject based on the ideXlab platform.
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An Efficient FPGA-Based Implementation for Quantized Remote Sensing Image Scene Classification Network
Electronics, 2020Co-Authors: Xiaoli Zhang, Xin Wei, Qianbo Sang, He Chen, Yizhuang XieAbstract:Deep Convolutional Neural Network (DCNN)-based image scene Classification models play an important role in a wide variety of remote sensing applications and achieve great success. However, the large-scale remote sensing images and the intensive computations make the deployment of these DCNN-based models on low-power processing systems (e.g., spaceborne or airborne) a challenging problem. To solve this problem, this paper proposes a high-performance Field-Programmable Gate Array (FPGA)-based DCNN accelerator by combining an efficient Network compression scheme and reasonable hardware architecture. Firstly, this paper applies the Network quantization to a high-accuracy remote sensing scene Classification Network, an improved oriented response Network (IORN). The volume of the parameters and feature maps in the Network is greatly reduced. Secondly, an efficient hardware architecture for Network implementation is proposed. The architecture employs dual-channel Double Data Rate Synchronous Dynamic Random-Access Memory (DDR) access mode, rational on-chip data processing scheme and efficient processing engine design. Finally, we implement the quantized IORN (Q-IORN) with the proposed architecture on a Xilinx VC709 development board. The experimental results show that the proposed accelerator has 88.31% top-1 Classification accuracy and achieves a throughput of 209.60 Giga-Operations Per Second (GOP/s) with a 6.32 W on-chip power consumption at 200 MHz. The comparison results with off-the-shelf devices and recent state-of-the-art implementations illustrate that the proposed accelerator has obvious advantages in terms of energy efficiency.
Wen Li - One of the best experts on this subject based on the ideXlab platform.
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deep reconstruction Classification Networks for unsupervised domain adaptation
European Conference on Computer Vision, 2016Co-Authors: Muhammad Ghifary, Bastiaan W Kleijn, Mengjie Zhang, David Balduzzi, Wen LiAbstract:In this paper, we propose a novel unsupervised domain adaptation algorithm based on deep learning for visual object recognition. Specifically, we design a new model called Deep Reconstruction-Classification Network (DRCN), which jointly learns a shared encoding representation for two tasks: (i) supervised Classification of labeled source data, and (ii) unsupervised reconstruction of unlabeled target data. In this way, the learnt representation not only preserves discriminability, but also encodes useful information from the target domain. Our new DRCN model can be optimized by using backpropagation similarly as the standard neural Networks.
Xiaoli Zhang - One of the best experts on this subject based on the ideXlab platform.
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An Efficient FPGA-Based Implementation for Quantized Remote Sensing Image Scene Classification Network
Electronics, 2020Co-Authors: Xiaoli Zhang, Xin Wei, Qianbo Sang, He Chen, Yizhuang XieAbstract:Deep Convolutional Neural Network (DCNN)-based image scene Classification models play an important role in a wide variety of remote sensing applications and achieve great success. However, the large-scale remote sensing images and the intensive computations make the deployment of these DCNN-based models on low-power processing systems (e.g., spaceborne or airborne) a challenging problem. To solve this problem, this paper proposes a high-performance Field-Programmable Gate Array (FPGA)-based DCNN accelerator by combining an efficient Network compression scheme and reasonable hardware architecture. Firstly, this paper applies the Network quantization to a high-accuracy remote sensing scene Classification Network, an improved oriented response Network (IORN). The volume of the parameters and feature maps in the Network is greatly reduced. Secondly, an efficient hardware architecture for Network implementation is proposed. The architecture employs dual-channel Double Data Rate Synchronous Dynamic Random-Access Memory (DDR) access mode, rational on-chip data processing scheme and efficient processing engine design. Finally, we implement the quantized IORN (Q-IORN) with the proposed architecture on a Xilinx VC709 development board. The experimental results show that the proposed accelerator has 88.31% top-1 Classification accuracy and achieves a throughput of 209.60 Giga-Operations Per Second (GOP/s) with a 6.32 W on-chip power consumption at 200 MHz. The comparison results with off-the-shelf devices and recent state-of-the-art implementations illustrate that the proposed accelerator has obvious advantages in terms of energy efficiency.