The Experts below are selected from a list of 16941 Experts worldwide ranked by ideXlab platform
Rui P. Martins - One of the best experts on this subject based on the ideXlab platform.
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a 550 mu w 20 khz bw 100 8 db sndr linear exponential multi bit incremental sigma delta adc with 256 Clock Cycles in 65 nm cmos
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Biao Wang, Franco Maloberti, U Sengpan, Rui P. MartinsAbstract:This paper presents an incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signal-to-quantization-noise ratio (SQNR) exponentially with a few number of Clock Cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniform-exponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2-V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 $\mu \text{W}$ , and 0.134 mm2, resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/−0.27 LSB and +0.84 LSB/−0.81 LSB, respectively.
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A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Biao Wang, Seng-pan U., Franco Maloberti, Rui P. MartinsAbstract:This paper presents an incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signal-to-quantization-noise ratio (SQNR) exponentially with a few number of Clock Cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniform-exponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2-V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 $\mu \text{W}$ , and 0.134 mm2, resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/−0.27 LSB and +0.84 LSB/−0.81 LSB, respectively.
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A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS
IEEE Journal of Solid-State Circuits, 2019Co-Authors: Biao Wang, Seng-pan U., Franco Maloberti, Rui P. MartinsAbstract:This paper presents an incremental analog-todigital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signalto-quantization-noise ratio (SQNR) exponentially with a few number of Clock Cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniformexponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 μW, and 0.134 mm2, resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/-0.27 LSB and +0.84 LSB/-0.81 LSB, respectively.
Biao Wang - One of the best experts on this subject based on the ideXlab platform.
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a 550 mu w 20 khz bw 100 8 db sndr linear exponential multi bit incremental sigma delta adc with 256 Clock Cycles in 65 nm cmos
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Biao Wang, Franco Maloberti, U Sengpan, Rui P. MartinsAbstract:This paper presents an incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signal-to-quantization-noise ratio (SQNR) exponentially with a few number of Clock Cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniform-exponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2-V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 $\mu \text{W}$ , and 0.134 mm2, resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/−0.27 LSB and +0.84 LSB/−0.81 LSB, respectively.
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A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Biao Wang, Seng-pan U., Franco Maloberti, Rui P. MartinsAbstract:This paper presents an incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signal-to-quantization-noise ratio (SQNR) exponentially with a few number of Clock Cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniform-exponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2-V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 $\mu \text{W}$ , and 0.134 mm2, resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/−0.27 LSB and +0.84 LSB/−0.81 LSB, respectively.
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A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS
IEEE Journal of Solid-State Circuits, 2019Co-Authors: Biao Wang, Seng-pan U., Franco Maloberti, Rui P. MartinsAbstract:This paper presents an incremental analog-todigital converter (IADC) with a two-phase linear-exponential accumulation loop. In the linear phase, the loop works as a first-order structure. The noise-coupling (NC) path is then enabled in the exponential phase thus boosting the signalto-quantization-noise ratio (SQNR) exponentially with a few number of Clock Cycles. The two-phase scheme combines the advantages of the thermal noise suppression in the first-order IADC and SQNR boosting in the exponential mode. The uniformexponential weight function allows the data weighted averaging (DWA) technique to work well, leading to the rotation of the multi-bit DAC mismatch error. Meanwhile, this scheme does not destroy the notches, which can be utilized to suppress the line noise. Implemented in 65-nm CMOS under 1.2V supply, the analog-to-digital converter (ADC) achieves an signal-to-noise + distortion ratio (SNDR)/dynamic range (DR) of 100.8 dB/101.8 dB with 20-kHz bandwidth (BW), 550 μW, and 0.134 mm2, resulting in Walden/Schreier FoMW/FoMS of 153 fJ/176.4 dB, respectively. The differential and integral nonlinearities are +0.27 LSB/-0.27 LSB and +0.84 LSB/-0.81 LSB, respectively.
Irith Pomeranz - One of the best experts on this subject based on the ideXlab platform.
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Padding of Multicycle Broadside and Skewed-Load Tests
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019Co-Authors: Irith PomeranzAbstract:Multicycle tests achieve test compaction by increasing the number of Clock Cycles between scan operations and reducing the number of tests. Tests in a compact multicycle test set typically have different numbers of Clock Cycles between their scan operations. This creates an opportunity to improve the test set by increasing the numbers of Clock Cycles between the scan operations of the tests, without increasing the number of tests and without exceeding a bound L on the number of Clock Cycles. Motivated by this observation, this paper studies the padding of multicycle broadside and skewed-load tests for transition faults. After padding, all the tests have L Clock Cycles between their scan operations. This paper makes several observations and defines new types of multicycle tests that are supported by commercial tools to allow padding to be performed without losing fault coverage. The new types of tests can be used for achieving a higher fault coverage, further test compaction, or an improved test set quality within the bound L. This paper develops padding procedures and presents experimental results for benchmark circuits to demonstrate these effects.
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ETS - Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests
2018 IEEE 23rd European Test Symposium (ETS), 2018Co-Authors: Irith PomeranzAbstract:Transition faults require scan tests with two functional Clock Cycles between a scan-in and a scan-out operation to activate the faults and propagate their effects to observable outputs. Multicycle tests, with two or more functional Clock Cycles between scan operations, provide the following advantages. (1) They potentially increase the defect coverage by exercising the circuit at-speed for several functional Clock Cycles. (2) They allow test compaction to be achieved. (3) Multicycle tests can address features such as multiple Clock domains and partial scan. (4) They create closer-to-functional operation conditions that are important for avoiding overtesting of delay faults.
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Covering undetected transition fault sites with optimistic unspecified transition faults under multicycle tests
2018 IEEE 23rd European Test Symposium (ETS), 2018Co-Authors: Irith PomeranzAbstract:Transition faults require scan tests with two functional Clock Cycles between a scan-in and a scan-out operation to activate the faults and propagate their effects to observable outputs. Multicycle tests, with two or more functional Clock Cycles between scan operations, provide the following advantages. (1) They potentially increase the defect coverage by exercising the circuit at-speed for several functional Clock Cycles. (2) They allow test compaction to be achieved. (3) Multicycle tests can address features such as multiple Clock domains and partial scan. (4) They create closer-to-functional operation conditions that are important for avoiding overtesting of delay faults.
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Multi-cycle broadside tests with runs of constant primary input vectors
IET Computers & Digital Techniques, 2014Co-Authors: Irith PomeranzAbstract:Multi-cycle tests, with two or more functional Clock Cycles between scan operations, can be used for test compaction. When tester limitations prevent primary input vectors from being changed at-speed, one of the possible solutions is to hold the primary input vector constant during the functional Clock Cycles of a multi-cycle test. However, this limits the level of test compaction that can be achieved. To provide an alternative to this solution, a new type of multi-cycle tests has been defined, where the primary input vector is changed during a Clock cycle that is applied under a slow Clock. This is followed by a run of the same vector applied under a fast Clock. Transition faults are activated during the Clock Cycles that are applied under a fast Clock. A test generation procedure that produces such test sets for transition faults has also been described. Experimental results demonstrate that the new type of tests can improve the ability to produce a compact test set for certain benchmark circuits.
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On the Switching Activity and Static Test Compaction of Multicycle Scan-Based Tests
IEEE Transactions on Computers, 2012Co-Authors: Irith PomeranzAbstract:Multicycle (multipattern) scan-based tests contain multiple Clock Cycles between scan operations. Each such Clock cycle defines a pattern of the test. Multipattern tests require fewer Clock Cycles for test application compared with single-pattern or two-pattern tests for the same target faults. In addition, this paper demonstrates that patterns appearing later in a test typically have lower switching activity than patterns appearing earlier in the test. Based on these observations, the paper presents a static test compaction procedure for multipattern tests that targets a reduction in switching activity while reducing the number of Clock Cycles required for test application. The procedure is based on an operation called test merging. Merging of a test pair causes the patterns from both tests to appear in a single test. By placing the patterns from a test with a high switching activity at the end of a merged test, their switching activity can be reduced. The proposed procedure combines the test merging procedure with a procedure that modifies a test set so as to reduce its switching activity. Through this procedure it takes advantage of the opportunities created by test merging to reduce the switching activity of patterns that appear later in a test.
S M Reddy - One of the best experts on this subject based on the ideXlab platform.
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at speed scan test with low switching activity
VLSI Test Symposium, 2010Co-Authors: Elham Moghaddam, Janusz Rajski, Mark Kassab, S M ReddyAbstract:This paper presents a novel method to generate test vectors that mimic functional operation from switching activity point of view. The method uses states obtained by applying a number of functional Clock Cycles starting from the scan-in state of a test vector to fill the unspecified scan cell values in test cubes. Experimental results presented for industrial circuits demonstrate the effectiveness of the proposed method.
Albert Y. Zomaya - One of the best experts on this subject based on the ideXlab platform.
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Statistical Regression to Predict Total Cumulative CPU Usage of MapReduce Jobs
arXiv: Distributed Parallel and Cluster Computing, 2013Co-Authors: Nikzad Babaii Rizvandi, Javid Taheri, Reza Moraveji, Albert Y. ZomayaAbstract:Recently, businesses have started using MapReduce as a popular computation framework for processing large amount of data, such as spam detection, and different data mining tasks, in both public and private clouds. Two of the challenging questions in such environments are (1) choosing suitable values for MapReduce configuration parameters e.g., number of mappers, number of reducers, and DFS block size, and (2) predicting the amount of resources that a user should lease from the service provider. Currently, the tasks of both choosing configuration parameters and estimating required resources are solely the users responsibilities. In this paper, we present an approach to provision the total CPU usage in Clock Cycles of jobs in MapReduce environment. For a MapReduce job, a profile of total CPU usage in Clock Cycles is built from the job past executions with different values of two configuration parameters e.g., number of mappers, and number of reducers. Then, a polynomial regression is used to model the relation between these configuration parameters and total CPU usage in Clock Cycles of the job. We also briefly study the influence of input data scaling on measured total CPU usage in Clock Cycles. This derived model along with the scaling result can then be used to provision the total CPU usage in Clock Cycles of the same jobs with different input data size. We validate the accuracy of our models using three realistic applications (WordCount, Exim MainLog parsing, and TeraSort). Results show that the predicted total CPU usage in Clock Cycles of generated resource provisioning options are less than 8% of the measured total CPU usage in Clock Cycles in our 20-node virtual Hadoop cluster.
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ICA3PP (1) - On modelling and prediction of total CPU usage for applications in mapreduce environments
Algorithms and Architectures for Parallel Processing, 2012Co-Authors: Nikzad Babaii Rizvandi, Javid Taheri, Reza Moraveji, Albert Y. ZomayaAbstract:Recently, businesses have started using MapReduce as a popular computation framework for processing large amount of data, such as spam detection, and different data mining tasks, in both public and private clouds. Two of the challenging questions in such environments are (1) choosing suitable values for MapReduce configuration parameters --- e.g., number of mappers, number of reducers, and DFS block size---, and (2) predicting the amount of resources that a user should lease from the service provider. Currently, the tasks of both choosing configuration parameters and estimating required resources are solely the users' responsibilities. In this paper, we present an approach to provision the total CPU usage in Clock Cycles of jobs in MapReduce environment. For a MapReduce job, a profile of total CPU usage in Clock Cycles is built from the job past executions with different values of two configuration parameters e.g., number of mappers, and number of reducers. Then, a polynomial regression is used to model the relation between these configuration parameters and total CPU usage in Clock Cycles of the job. We also briefly study the influence of input data scaling on measured total CPU usage in Clock Cycles. This derived model along with the scaling result can then be used to provision the total CPU usage in Clock Cycles of the same jobs with different input data size. We validate the accuracy of our models using three realistic applications (WordCount, Exim MainLog parsing, and TeraSort). Results show that the predicted total CPU usage in Clock Cycles of generated resource provisioning options are less than 8% of the measured total CPU usage in Clock Cycles in our 20-node virtual Hadoop cluster.
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On Modelling and Prediction of Total CPU Usage for Applications in MapReduce Environments
arXiv: Distributed Parallel and Cluster Computing, 2012Co-Authors: Nikzad Babaii Rizvandi, Javid Taheri, Reza Moraveji, Albert Y. ZomayaAbstract:Recently, businesses have started using MapReduce as a popular computation framework for processing large amount of data, such as spam detection, and different data mining tasks, in both public and private clouds. Two of the challenging questions in such environments are (1) choosing suitable values for MapReduce configuration parameters -e.g., number of mappers, number of reducers, and DFS block size-, and (2) predicting the amount of resources that a user should lease from the service provider. Currently, the tasks of both choosing configuration parameters and estimating required resources are solely the users' responsibilities. In this paper, we present an approach to provision the total CPU usage in Clock Cycles of jobs in MapReduce environment. For a MapReduce job, a profile of total CPU usage in Clock Cycles is built from the job past executions with different values of two configuration parameters e.g., number of mappers, and number of reducers. Then, a polynomial regression is used to model the relation between these configuration parameters and total CPU usage in Clock Cycles of the job. We also briefly study the influence of input data scaling on measured total CPU usage in Clock Cycles. This derived model along with the scaling result can then be used to provision the total CPU usage in Clock Cycles of the same jobs with different input data size. We validate the accuracy of our models using three realistic applications (WordCount, Exim MainLog parsing, and TeraSort). Results show that the predicted total CPU usage in Clock Cycles of generated resource provisioning options are less than 8% of the measured total CPU usage in Clock Cycles in our 20-node virtual Hadoop cluster.
