The Experts below are selected from a list of 108 Experts worldwide ranked by ideXlab platform

Patrick Crowley - One of the best experts on this subject based on the ideXlab platform.

  • exploiting coarse grained Parallelism to accelerate protein motif finding with a network processor
    International Conference on Parallel Architectures and Compilation Techniques, 2005
    Co-Authors: B Wun, Jeremy Buhler, Patrick Crowley
    Abstract:

    While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures since the late 1990s. NPs differ qualitatively from workstation and server CMPs in that they replicate many simple, highly efficient processor cores on a chip, rather than a small number of sophisticated superscalar CPUs. In this paper, we compare the performance of one such NP, the Intel IXP 2850, to that of the Intel Pentium 4 when executing a scientific computing workload with a high degree of thread-level Parallelism. Our target program, HMMer, is a bioinformatics tool that identifies conserved motifs in protein sequences. HMMer represents motifs as hidden Markov models (HMMs) and spends most of its time executing the well-known Viterbi algorithm to align proteins to these models. Our observations of HMMer on the IXP are therefore relevant to computations in many other domains that rely on the Viterbi algorithm. We show that the IXP achieves a speedup of 1.82 over the Pentium, despite the Pentium's 1.85x faster clock. Moreover, we argue that next-generation IXP NPs will likely provide a 10-20x speedup for our workload over the IXP 2850, in contrast to 5-1Ox speedup expected from a next-generation Pentium-based CMP.

Krzysztof Siedlecki - One of the best experts on this subject based on the ideXlab platform.

  • coarse grained loop parallelization iteration space slicing vs affine transformations
    Parallel Computing, 2011
    Co-Authors: Anna Beletska, Marek Palkowski, Wlodzimierz Bielecki, Albert Cohen, Krzysztof Siedlecki
    Abstract:

    Automatic Coarse-Grained parallelization of program loops is of great importance for parallel computing systems. This paper presents the theory of Iteration Space Slicing aimed at extracting synchronization-free Parallelism available in arbitrarily nested program loops. We demonstrate that Iteration Space Slicing algorithms permits for extracting more Coarse-Grained Parallelism than that extracted by means of the Affine Transformation Framework provided that we are able to calculate the transitive closure of the union of relations describing all dependences in the affine loop. Experimental results show that by means of Iteration Space Slicing algorithms, we are able to extract Coarse-Grained Parallelism for many loops of NAS and UTDSP benchmarks. Problems to be resolved in order to enhance the theory of Iteration Space Slicing are discussed.

  • coarse grained loop parallelization iteration space slicing vs affine transformations
    International Symposium on Parallel and Distributed Computing, 2009
    Co-Authors: Anna Beletska, Marek Palkowski, Wlodzimierz Bielecki, Albert Cohen, Krzysztof Siedlecki
    Abstract:

    Automatic Coarse-Grained parallelization of program loops is of great importance for multi-core computing systems. This paper presents a comparison of Iteration SpaceSlicing and Affine Transformation Framework algorithms aimed at extracting Coarse-Grained Parallelism available in arbitrarily nested parameterized affine loops. We demonstrate that Iteration Space Slicing permits for extracting more Coarse-Grained Parallelism in comparison to the Affine Transformation Framework. Experimental results show that by means of Iteration SpaceSlicing algorithms, we are able to extract Coarse-Grained Parallelism for most loops of the NAS and UTDSP benchmarks, and that there is a strong need in devising advanced algorithms for calculating the exact transitive closure of dependence relations in order to increase the applicability of that framework.

Saman Amarasinghe - One of the best experts on this subject based on the ideXlab platform.

  • exploiting coarse grained task data and pipeline Parallelism in stream programs
    Architectural Support for Programming Languages and Operating Systems, 2006
    Co-Authors: Michael I Gordon, William Thies, Saman Amarasinghe
    Abstract:

    As multicore architectures enter the mainstream, there is a pressing demand for high-level programming models that can effectively map to them. Stream programming offers an attractive way to expose Coarse-Grained Parallelism, as streaming applications (image, video, DSP, etc.) are naturally represented by independent filters that communicate over explicit data channels.In this paper, we demonstrate an end-to-end stream compiler that attains robust multicore performance in the face of varying application characteristics. As benchmarks exhibit different amounts of task, data, and pipeline Parallelism, we exploit all types of Parallelism in a unified manner in order to achieve this generality. Our compiler, which maps from the StreamIt language to the 16-core Raw architecture, attains a 11.2x mean speedup over a single-core baseline, and a 1.84x speedup over our previous work.

Wlodzimierz Bielecki - One of the best experts on this subject based on the ideXlab platform.

  • extracting coarse grained Parallelism for affine perfectly nested quasi uniform loops
    Parallel Processing and Applied Mathematics, 2011
    Co-Authors: Wlodzimierz Bielecki, Krzysztof Kraska
    Abstract:

    This paper presents a new approach for the extraction of coarse---grained Parallelism available in program loops. The approach permits for extracting Parallelism for both uniform and quasi---uniform perfectly nested parameterized loops, where the loop bounds and data accesses are affine functions of loop indices and symbolic parameters. It extracts a set of synchronization---free code fragments. The procedure has a polynomial time complexity except for one step of calculations. The effectiveness and time complexity of the approach are evaluated by means of loops of the NAS Parallel Benchmark suite.

  • coarse grained loop parallelization iteration space slicing vs affine transformations
    Parallel Computing, 2011
    Co-Authors: Anna Beletska, Marek Palkowski, Wlodzimierz Bielecki, Albert Cohen, Krzysztof Siedlecki
    Abstract:

    Automatic Coarse-Grained parallelization of program loops is of great importance for parallel computing systems. This paper presents the theory of Iteration Space Slicing aimed at extracting synchronization-free Parallelism available in arbitrarily nested program loops. We demonstrate that Iteration Space Slicing algorithms permits for extracting more Coarse-Grained Parallelism than that extracted by means of the Affine Transformation Framework provided that we are able to calculate the transitive closure of the union of relations describing all dependences in the affine loop. Experimental results show that by means of Iteration Space Slicing algorithms, we are able to extract Coarse-Grained Parallelism for many loops of NAS and UTDSP benchmarks. Problems to be resolved in order to enhance the theory of Iteration Space Slicing are discussed.

  • coarse grained loop parallelization iteration space slicing vs affine transformations
    International Symposium on Parallel and Distributed Computing, 2009
    Co-Authors: Anna Beletska, Marek Palkowski, Wlodzimierz Bielecki, Albert Cohen, Krzysztof Siedlecki
    Abstract:

    Automatic Coarse-Grained parallelization of program loops is of great importance for multi-core computing systems. This paper presents a comparison of Iteration SpaceSlicing and Affine Transformation Framework algorithms aimed at extracting Coarse-Grained Parallelism available in arbitrarily nested parameterized affine loops. We demonstrate that Iteration Space Slicing permits for extracting more Coarse-Grained Parallelism in comparison to the Affine Transformation Framework. Experimental results show that by means of Iteration SpaceSlicing algorithms, we are able to extract Coarse-Grained Parallelism for most loops of the NAS and UTDSP benchmarks, and that there is a strong need in devising advanced algorithms for calculating the exact transitive closure of dependence relations in order to increase the applicability of that framework.

B Wun - One of the best experts on this subject based on the ideXlab platform.

  • exploiting coarse grained Parallelism to accelerate protein motif finding with a network processor
    International Conference on Parallel Architectures and Compilation Techniques, 2005
    Co-Authors: B Wun, Jeremy Buhler, Patrick Crowley
    Abstract:

    While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures since the late 1990s. NPs differ qualitatively from workstation and server CMPs in that they replicate many simple, highly efficient processor cores on a chip, rather than a small number of sophisticated superscalar CPUs. In this paper, we compare the performance of one such NP, the Intel IXP 2850, to that of the Intel Pentium 4 when executing a scientific computing workload with a high degree of thread-level Parallelism. Our target program, HMMer, is a bioinformatics tool that identifies conserved motifs in protein sequences. HMMer represents motifs as hidden Markov models (HMMs) and spends most of its time executing the well-known Viterbi algorithm to align proteins to these models. Our observations of HMMer on the IXP are therefore relevant to computations in many other domains that rely on the Viterbi algorithm. We show that the IXP achieves a speedup of 1.82 over the Pentium, despite the Pentium's 1.85x faster clock. Moreover, we argue that next-generation IXP NPs will likely provide a 10-20x speedup for our workload over the IXP 2850, in contrast to 5-1Ox speedup expected from a next-generation Pentium-based CMP.