The Experts below are selected from a list of 90504 Experts worldwide ranked by ideXlab platform

Rainer G Spallek - One of the best experts on this subject based on the ideXlab platform.

  • improving Code Efficiency for reconfigurable vliw processors
    International Parallel and Distributed Processing Symposium, 2002
    Co-Authors: S Kohler, J Braunes, Sergei Sawitzki, Rainer G Spallek
    Abstract:

    High Code Efficiency (operations per instruction) combined with a high degree of instruction level parallelism can rarely be obtained by hardwired microprocessor designs for a broad application domain. The implementation of reconfigurable execution units is a promising way to enhance Code Efficiency and microprocessor performance. However, the unit reconfiguration process introduces an additional dimension to the Code generation phase, which complicates scheduling and may lead to Code deficiencies if resource conflicts occure. This paper discusses Code generation issues for a runtime-reconfigurable VLIW processor model, which combines fixed and flexible functional units (FU) in one template. Reconfigurable units (RFU) can be adapted to the application demands exploiting more coarse-grain parallelism than common instruction-level FUs. A case study illustrates the extraction of conditions for reconfigurable instructions proves scheduling possibilities for a set of common DSP benchmark algorithms. The software environment described includes a retargetable, parallelizing C compiler based on the SUIF compiler kit and a simulator, which can be used for identifying application-specific SIMD-instruction candidates and for evaluating the runtime behavior of the created object Code.

  • IPDPS - Improving Code Efficiency for reconfigurable VLIW processors
    Proceedings 16th International Parallel and Distributed Processing Symposium, 2002
    Co-Authors: S Kohler, J Braunes, Sergei Sawitzki, Rainer G Spallek
    Abstract:

    High Code Efficiency (operations per instruction) combined with a high degree of instruction level parallelism can rarely be obtained by hardwired microprocessor designs for a broad application domain. The implementation of reconfigurable execution units is a promising way to enhance Code Efficiency and microprocessor performance. However, the unit reconfiguration process introduces an additional dimension to the Code generation phase, which complicates scheduling and may lead to Code deficiencies if resource conflicts occure. This paper discusses Code generation issues for a runtime-reconfigurable VLIW processor model, which combines fixed and flexible functional units (FU) in one template. Reconfigurable units (RFU) can be adapted to the application demands exploiting more coarse-grain parallelism than common instruction-level FUs. A case study illustrates the extraction of conditions for reconfigurable instructions proves scheduling possibilities for a set of common DSP benchmark algorithms. The software environment described includes a retargetable, parallelizing C compiler based on the SUIF compiler kit and a simulator, which can be used for identifying application-specific SIMD-instruction candidates and for evaluating the runtime behavior of the created object Code.

S Kohler - One of the best experts on this subject based on the ideXlab platform.

  • improving Code Efficiency for reconfigurable vliw processors
    International Parallel and Distributed Processing Symposium, 2002
    Co-Authors: S Kohler, J Braunes, Sergei Sawitzki, Rainer G Spallek
    Abstract:

    High Code Efficiency (operations per instruction) combined with a high degree of instruction level parallelism can rarely be obtained by hardwired microprocessor designs for a broad application domain. The implementation of reconfigurable execution units is a promising way to enhance Code Efficiency and microprocessor performance. However, the unit reconfiguration process introduces an additional dimension to the Code generation phase, which complicates scheduling and may lead to Code deficiencies if resource conflicts occure. This paper discusses Code generation issues for a runtime-reconfigurable VLIW processor model, which combines fixed and flexible functional units (FU) in one template. Reconfigurable units (RFU) can be adapted to the application demands exploiting more coarse-grain parallelism than common instruction-level FUs. A case study illustrates the extraction of conditions for reconfigurable instructions proves scheduling possibilities for a set of common DSP benchmark algorithms. The software environment described includes a retargetable, parallelizing C compiler based on the SUIF compiler kit and a simulator, which can be used for identifying application-specific SIMD-instruction candidates and for evaluating the runtime behavior of the created object Code.

  • IPDPS - Improving Code Efficiency for reconfigurable VLIW processors
    Proceedings 16th International Parallel and Distributed Processing Symposium, 2002
    Co-Authors: S Kohler, J Braunes, Sergei Sawitzki, Rainer G Spallek
    Abstract:

    High Code Efficiency (operations per instruction) combined with a high degree of instruction level parallelism can rarely be obtained by hardwired microprocessor designs for a broad application domain. The implementation of reconfigurable execution units is a promising way to enhance Code Efficiency and microprocessor performance. However, the unit reconfiguration process introduces an additional dimension to the Code generation phase, which complicates scheduling and may lead to Code deficiencies if resource conflicts occure. This paper discusses Code generation issues for a runtime-reconfigurable VLIW processor model, which combines fixed and flexible functional units (FU) in one template. Reconfigurable units (RFU) can be adapted to the application demands exploiting more coarse-grain parallelism than common instruction-level FUs. A case study illustrates the extraction of conditions for reconfigurable instructions proves scheduling possibilities for a set of common DSP benchmark algorithms. The software environment described includes a retargetable, parallelizing C compiler based on the SUIF compiler kit and a simulator, which can be used for identifying application-specific SIMD-instruction candidates and for evaluating the runtime behavior of the created object Code.

G. Mclean - One of the best experts on this subject based on the ideXlab platform.

  • Development of a generic crop model template in the cropping system model APSIM
    European Journal of Agronomy, 2002
    Co-Authors: Enli Wang, M. J. Robertson, G. L. Hammer, P.s. Carberry, Dean Holzworth, Holger Meinke, Sc C. Chapman, J. N. G. Hargreaves, N. I. Huth, G. Mclean
    Abstract:

    The Agricultural Production Systems slMulator, APSIM, is a cropping system modelling environment that simulates the dynamics of soil-plant-management interactions within a single crop or a cropping system. Adaptation of previously developed crop models has resulted in multiple crop modules in APSIM, which have low scientific transparency and Code Efficiency. A generic crop model template (GCROP) has been developed to capture unifying physiological principles across crops (plant types) and to provide modular and efficient Code for crop modelling. It comprises a standard crop interface to the APSIM engine, a generic crop model structure, a crop process library, and well-structured crop parameter files. The process library contains the major science underpinning the crop models and incorporates generic routines based on physiological principles for growth and development processes that are common across crops. It allows APSIM to simulate different crops using the same set of computer Code. The generic model structure and parameter files provide an easy way to test, modify, exchange and compare modelling approaches at process level without necessitating changes in the Code. The standard interface generalises the model inputs and outputs, and utilises a standard protocol to communicate with other APSIM modules through the APSIM engine. The crop template serves as a convenient means to test new insights and compare approaches to component modelling, while maintaining a focus on predictive capability. This paper describes and discusses the scientific basis, the design, implementation and future development of the crop template in APSIM. On this basis, we argue that the combination of good software engineering with sound crop science can enhance the rate of advance in crop modelling. Crown Copyright (C) 2002 Published by Elsevier Science B.V. All rights reserved.

J Braunes - One of the best experts on this subject based on the ideXlab platform.

  • improving Code Efficiency for reconfigurable vliw processors
    International Parallel and Distributed Processing Symposium, 2002
    Co-Authors: S Kohler, J Braunes, Sergei Sawitzki, Rainer G Spallek
    Abstract:

    High Code Efficiency (operations per instruction) combined with a high degree of instruction level parallelism can rarely be obtained by hardwired microprocessor designs for a broad application domain. The implementation of reconfigurable execution units is a promising way to enhance Code Efficiency and microprocessor performance. However, the unit reconfiguration process introduces an additional dimension to the Code generation phase, which complicates scheduling and may lead to Code deficiencies if resource conflicts occure. This paper discusses Code generation issues for a runtime-reconfigurable VLIW processor model, which combines fixed and flexible functional units (FU) in one template. Reconfigurable units (RFU) can be adapted to the application demands exploiting more coarse-grain parallelism than common instruction-level FUs. A case study illustrates the extraction of conditions for reconfigurable instructions proves scheduling possibilities for a set of common DSP benchmark algorithms. The software environment described includes a retargetable, parallelizing C compiler based on the SUIF compiler kit and a simulator, which can be used for identifying application-specific SIMD-instruction candidates and for evaluating the runtime behavior of the created object Code.

  • IPDPS - Improving Code Efficiency for reconfigurable VLIW processors
    Proceedings 16th International Parallel and Distributed Processing Symposium, 2002
    Co-Authors: S Kohler, J Braunes, Sergei Sawitzki, Rainer G Spallek
    Abstract:

    High Code Efficiency (operations per instruction) combined with a high degree of instruction level parallelism can rarely be obtained by hardwired microprocessor designs for a broad application domain. The implementation of reconfigurable execution units is a promising way to enhance Code Efficiency and microprocessor performance. However, the unit reconfiguration process introduces an additional dimension to the Code generation phase, which complicates scheduling and may lead to Code deficiencies if resource conflicts occure. This paper discusses Code generation issues for a runtime-reconfigurable VLIW processor model, which combines fixed and flexible functional units (FU) in one template. Reconfigurable units (RFU) can be adapted to the application demands exploiting more coarse-grain parallelism than common instruction-level FUs. A case study illustrates the extraction of conditions for reconfigurable instructions proves scheduling possibilities for a set of common DSP benchmark algorithms. The software environment described includes a retargetable, parallelizing C compiler based on the SUIF compiler kit and a simulator, which can be used for identifying application-specific SIMD-instruction candidates and for evaluating the runtime behavior of the created object Code.

Sergei Sawitzki - One of the best experts on this subject based on the ideXlab platform.

  • improving Code Efficiency for reconfigurable vliw processors
    International Parallel and Distributed Processing Symposium, 2002
    Co-Authors: S Kohler, J Braunes, Sergei Sawitzki, Rainer G Spallek
    Abstract:

    High Code Efficiency (operations per instruction) combined with a high degree of instruction level parallelism can rarely be obtained by hardwired microprocessor designs for a broad application domain. The implementation of reconfigurable execution units is a promising way to enhance Code Efficiency and microprocessor performance. However, the unit reconfiguration process introduces an additional dimension to the Code generation phase, which complicates scheduling and may lead to Code deficiencies if resource conflicts occure. This paper discusses Code generation issues for a runtime-reconfigurable VLIW processor model, which combines fixed and flexible functional units (FU) in one template. Reconfigurable units (RFU) can be adapted to the application demands exploiting more coarse-grain parallelism than common instruction-level FUs. A case study illustrates the extraction of conditions for reconfigurable instructions proves scheduling possibilities for a set of common DSP benchmark algorithms. The software environment described includes a retargetable, parallelizing C compiler based on the SUIF compiler kit and a simulator, which can be used for identifying application-specific SIMD-instruction candidates and for evaluating the runtime behavior of the created object Code.

  • IPDPS - Improving Code Efficiency for reconfigurable VLIW processors
    Proceedings 16th International Parallel and Distributed Processing Symposium, 2002
    Co-Authors: S Kohler, J Braunes, Sergei Sawitzki, Rainer G Spallek
    Abstract:

    High Code Efficiency (operations per instruction) combined with a high degree of instruction level parallelism can rarely be obtained by hardwired microprocessor designs for a broad application domain. The implementation of reconfigurable execution units is a promising way to enhance Code Efficiency and microprocessor performance. However, the unit reconfiguration process introduces an additional dimension to the Code generation phase, which complicates scheduling and may lead to Code deficiencies if resource conflicts occure. This paper discusses Code generation issues for a runtime-reconfigurable VLIW processor model, which combines fixed and flexible functional units (FU) in one template. Reconfigurable units (RFU) can be adapted to the application demands exploiting more coarse-grain parallelism than common instruction-level FUs. A case study illustrates the extraction of conditions for reconfigurable instructions proves scheduling possibilities for a set of common DSP benchmark algorithms. The software environment described includes a retargetable, parallelizing C compiler based on the SUIF compiler kit and a simulator, which can be used for identifying application-specific SIMD-instruction candidates and for evaluating the runtime behavior of the created object Code.