The Experts below are selected from a list of 285 Experts worldwide ranked by ideXlab platform
A. Evans - One of the best experts on this subject based on the ideXlab platform.
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IRPS - Techniques for heavy ion microbeam analysis of FPGA SER sensitivty
2015 IEEE International Reliability Physics Symposium, 2015Co-Authors: A. Evans, Dan Alexandrescu, Veronique Ferlet-cavrois, Kay-obbe VossAbstract:Using the heavy-ion micro-probe facility at GSI in Darmstadt, individual heavy ions can be targeted at specific locations on a die. Circuits to measure SEUs in flip-flops and RAMs, SETs in Combinatorial Logic and glitches in PLLs were developed and tested. Detailed results for a study of the 130 nm ProASIC3L FPGA tested under Au (94 MeV/mg /cm2) and Ti (19 MeV/mg / cm2) ions are presented.
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new approaches for synthesis of redundant Combinatorial Logic for selective fault tolerance
International On-Line Testing Symposium, 2014Co-Authors: Hao Xie, A. Evans, Lin Chen, Shi-jie Wen, Rui Liu, Dan Alexandrescu, Rick WongAbstract:With shrinking process technologies, the likelihood of mid-life faults in Combinatorial Logic is increasing. Approximate Logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating approximate Logic functions. The algorithm considers the failure probabilities of the gates and it uses a sum of product (SOP) representation. The results on some circuits show that FIT rate can be reduced by 75% with an area penalty of 46% and inserting only two additional layers of Logic.
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IOLTS - New approaches for synthesis of redundant Combinatorial Logic for selective fault tolerance
2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014Co-Authors: Hao Xie, A. Evans, Lin Chen, Shi-jie Wen, Rui Liu, Dan Alexandrescu, Rick WongAbstract:With shrinking process technologies, the likelihood of mid-life faults in Combinatorial Logic is increasing. Approximate Logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating approximate Logic functions. The algorithm considers the failure probabilities of the gates and it uses a sum of product (SOP) representation. The results on some circuits show that FIT rate can be reduced by 75% with an area penalty of 46% and inserting only two additional layers of Logic.
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Synthesis of Redundant Combinatorial Logic for Selective Fault Tolerance
2013Co-Authors: A. Evans, Hao Xie, Lin ChenAbstract:With shrinking process technologies, the likelihood of mid-life Logic faults is increasing. In this paper, we present an approach for mitigating the effects of faults in Combinatorial Logic through the selective addition of redundant Logic. This approach can be applied to a generic digital circuit, protects against multiple fault models and offers a trade-off between area and fault coverage. The results show that fault coverage can be improved by 4x with an area penalty of 50% and only two additional layers of Logic.
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PRDC - Synthesis of Redundant Combinatorial Logic for Selective Fault Tolerance
2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013Co-Authors: Hao Xie, A. Evans, Lin Chen, Shi-jie Wen, Rick WongAbstract:With shrinking process technologies, the likelihood of mid-life Logic faults is increasing. In this paper, we present an approach for mitigating the effects of faults in Combinatorial Logic through the selective addition of redundant Logic. This approach can be applied to a generic digital circuit, protects against multiple fault models and offers a trade-off between area and fault coverage. The results show that fault coverage can be improved by 4x with an area penalty of 50% and only two additional layers of Logic.
Philippe Roche - One of the best experts on this subject based on the ideXlab platform.
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an approach to reduce computational cost in Combinatorial Logic netlist reliability analysis using circuit clustering and conditional probabilities
International On-Line Testing Symposium, 2011Co-Authors: Josep Torras Flaquer, Jeanmarc Daveau, Lirida Alves De Barros Naviner, Philippe RocheAbstract:We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of Combinatorial Logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.
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IOLTS - An approach to reduce computational cost in Combinatorial Logic netlist reliability analysis using circuit clustering and conditional probabilities
2011 IEEE 17th International On-Line Testing Symposium, 2011Co-Authors: Josep Torras Flaquer, Jeanmarc Daveau, Lirida Alves De Barros Naviner, Philippe RocheAbstract:We propose a novel approach relying on signal state conditional probabilities and circuit clustering to perform a probabilistic analytical estimation of the reliability of Combinatorial Logic circuits. This approach uses clustering and joint conditional probabilities to reduce the execution time and matrix size needed. Its effectiveness is demonstrated on a 8 bit Brent Kung adder.
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handling reconvergent paths using conditional probabilities in Combinatorial Logic netlist reliability estimation
International Conference on Electronics Circuits and Systems, 2010Co-Authors: Josep Torras Flaquer, Jeanmarc Daveau, Lirida Alves De Barros Naviner, Philippe RocheAbstract:Reliability analysis, SET and SER estimation in Combinatorial Logic circuits rely on various techniques ranging from SPICE simulation to probabilistic error propagation models. Signal correlations are known to be a source of error in many approaches. Such correlations are created between signals on different branches of a reconvergent path. We propose in this paper to use conditioned probabilities to handle such correlation and show that it allows achieving a correct result.
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fast reliability analysis of Combinatorial Logic circuits using conditional probabilities
Microelectronics Reliability, 2010Co-Authors: Jeanmarc Daveau, Lirida Alves De Barros Naviner, Torras J Flaquer, Philippe RocheAbstract:Probabilistic reliability analysis is a common approach in Logic circuit reliability analysis. Existing methods suffer from accuracy or scalability problems for large circuits because of Combinatorial explosion. In this work we show how the use of conditional probabilities can overcome scalability problems while maintaining accurate reliability estimation. The source of accuracy and scalability problems in these approaches is the presence of reconverging signals. An efficient use of conditional probabilities used to decorrelate signals allows for fast and accurate reliability analysis.
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ICECS - Handling reconvergent paths using conditional probabilities in Combinatorial Logic netlist reliability estimation
2010 17th IEEE International Conference on Electronics Circuits and Systems, 2010Co-Authors: Josep Torras Flaquer, Jeanmarc Daveau, Lirida Alves De Barros Naviner, Philippe RocheAbstract:Reliability analysis, SET and SER estimation in Combinatorial Logic circuits rely on various techniques ranging from SPICE simulation to probabilistic error propagation models. Signal correlations are known to be a source of error in many approaches. Such correlations are created between signals on different branches of a reconvergent path. We propose in this paper to use conditioned probabilities to handle such correlation and show that it allows achieving a correct result.
Rick Wong - One of the best experts on this subject based on the ideXlab platform.
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new approaches for synthesis of redundant Combinatorial Logic for selective fault tolerance
International On-Line Testing Symposium, 2014Co-Authors: Hao Xie, A. Evans, Lin Chen, Shi-jie Wen, Rui Liu, Dan Alexandrescu, Rick WongAbstract:With shrinking process technologies, the likelihood of mid-life faults in Combinatorial Logic is increasing. Approximate Logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating approximate Logic functions. The algorithm considers the failure probabilities of the gates and it uses a sum of product (SOP) representation. The results on some circuits show that FIT rate can be reduced by 75% with an area penalty of 46% and inserting only two additional layers of Logic.
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IOLTS - New approaches for synthesis of redundant Combinatorial Logic for selective fault tolerance
2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014Co-Authors: Hao Xie, A. Evans, Lin Chen, Shi-jie Wen, Rui Liu, Dan Alexandrescu, Rick WongAbstract:With shrinking process technologies, the likelihood of mid-life faults in Combinatorial Logic is increasing. Approximate Logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating approximate Logic functions. The algorithm considers the failure probabilities of the gates and it uses a sum of product (SOP) representation. The results on some circuits show that FIT rate can be reduced by 75% with an area penalty of 46% and inserting only two additional layers of Logic.
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PRDC - Synthesis of Redundant Combinatorial Logic for Selective Fault Tolerance
2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013Co-Authors: Hao Xie, A. Evans, Lin Chen, Shi-jie Wen, Rick WongAbstract:With shrinking process technologies, the likelihood of mid-life Logic faults is increasing. In this paper, we present an approach for mitigating the effects of faults in Combinatorial Logic through the selective addition of redundant Logic. This approach can be applied to a generic digital circuit, protects against multiple fault models and offers a trade-off between area and fault coverage. The results show that fault coverage can be improved by 4x with an area penalty of 50% and only two additional layers of Logic.
Dan Alexandrescu - One of the best experts on this subject based on the ideXlab platform.
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IRPS - Techniques for heavy ion microbeam analysis of FPGA SER sensitivty
2015 IEEE International Reliability Physics Symposium, 2015Co-Authors: A. Evans, Dan Alexandrescu, Veronique Ferlet-cavrois, Kay-obbe VossAbstract:Using the heavy-ion micro-probe facility at GSI in Darmstadt, individual heavy ions can be targeted at specific locations on a die. Circuits to measure SEUs in flip-flops and RAMs, SETs in Combinatorial Logic and glitches in PLLs were developed and tested. Detailed results for a study of the 130 nm ProASIC3L FPGA tested under Au (94 MeV/mg /cm2) and Ti (19 MeV/mg / cm2) ions are presented.
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new approaches for synthesis of redundant Combinatorial Logic for selective fault tolerance
International On-Line Testing Symposium, 2014Co-Authors: Hao Xie, A. Evans, Lin Chen, Shi-jie Wen, Rui Liu, Dan Alexandrescu, Rick WongAbstract:With shrinking process technologies, the likelihood of mid-life faults in Combinatorial Logic is increasing. Approximate Logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating approximate Logic functions. The algorithm considers the failure probabilities of the gates and it uses a sum of product (SOP) representation. The results on some circuits show that FIT rate can be reduced by 75% with an area penalty of 46% and inserting only two additional layers of Logic.
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IOLTS - New approaches for synthesis of redundant Combinatorial Logic for selective fault tolerance
2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014Co-Authors: Hao Xie, A. Evans, Lin Chen, Shi-jie Wen, Rui Liu, Dan Alexandrescu, Rick WongAbstract:With shrinking process technologies, the likelihood of mid-life faults in Combinatorial Logic is increasing. Approximate Logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating approximate Logic functions. The algorithm considers the failure probabilities of the gates and it uses a sum of product (SOP) representation. The results on some circuits show that FIT rate can be reduced by 75% with an area penalty of 46% and inserting only two additional layers of Logic.
Hao Xie - One of the best experts on this subject based on the ideXlab platform.
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new approaches for synthesis of redundant Combinatorial Logic for selective fault tolerance
International On-Line Testing Symposium, 2014Co-Authors: Hao Xie, A. Evans, Lin Chen, Shi-jie Wen, Rui Liu, Dan Alexandrescu, Rick WongAbstract:With shrinking process technologies, the likelihood of mid-life faults in Combinatorial Logic is increasing. Approximate Logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating approximate Logic functions. The algorithm considers the failure probabilities of the gates and it uses a sum of product (SOP) representation. The results on some circuits show that FIT rate can be reduced by 75% with an area penalty of 46% and inserting only two additional layers of Logic.
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IOLTS - New approaches for synthesis of redundant Combinatorial Logic for selective fault tolerance
2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014Co-Authors: Hao Xie, A. Evans, Lin Chen, Shi-jie Wen, Rui Liu, Dan Alexandrescu, Rick WongAbstract:With shrinking process technologies, the likelihood of mid-life faults in Combinatorial Logic is increasing. Approximate Logic functions are a promising approach to mitigate such faults as the technique can be applied to any digital circuit, it protects against multiple fault models and offers a trade-off between increased area and fault coverage. In this paper we present a new algorithm for generating approximate Logic functions. The algorithm considers the failure probabilities of the gates and it uses a sum of product (SOP) representation. The results on some circuits show that FIT rate can be reduced by 75% with an area penalty of 46% and inserting only two additional layers of Logic.
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Synthesis of Redundant Combinatorial Logic for Selective Fault Tolerance
2013Co-Authors: A. Evans, Hao Xie, Lin ChenAbstract:With shrinking process technologies, the likelihood of mid-life Logic faults is increasing. In this paper, we present an approach for mitigating the effects of faults in Combinatorial Logic through the selective addition of redundant Logic. This approach can be applied to a generic digital circuit, protects against multiple fault models and offers a trade-off between area and fault coverage. The results show that fault coverage can be improved by 4x with an area penalty of 50% and only two additional layers of Logic.
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PRDC - Synthesis of Redundant Combinatorial Logic for Selective Fault Tolerance
2013 IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013Co-Authors: Hao Xie, A. Evans, Lin Chen, Shi-jie Wen, Rick WongAbstract:With shrinking process technologies, the likelihood of mid-life Logic faults is increasing. In this paper, we present an approach for mitigating the effects of faults in Combinatorial Logic through the selective addition of redundant Logic. This approach can be applied to a generic digital circuit, protects against multiple fault models and offers a trade-off between area and fault coverage. The results show that fault coverage can be improved by 4x with an area penalty of 50% and only two additional layers of Logic.