The Experts below are selected from a list of 50739 Experts worldwide ranked by ideXlab platform
Hideharu Amano - One of the best experts on this subject based on the ideXlab platform.
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Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors
IEEE Transactions on Computers, 2011Co-Authors: Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, Tsutomu YoshinagaAbstract:Multi and many-core applications are sensitive to interprocessor Communication latencies, suggesting the need for low-Latency on-chip networks. We propose a low-Latency router architecture that predicts the output channel to be used by the next packet transfer and speculatively completes the switch arbitration to reduce Communication Latency. The packets coming into the prediction routers are transferred without waiting for the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing Communication Latency is the hit rates of the prediction algorithms, which vary based on network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-Latency routers that skip one or more pipeline stages use a bypass data path that is based on a static or single bypassing policy (e.g., accelerating the packets moving in the same dimension), our prediction router architecture predictively forwards packets based on the prediction algorithm selected from among several candidates in response to the network environment. We analyze the prediction hit rates of five prediction algorithms on meshes, tori, fat trees, and Spidergons. Then, we present four case studies, each of which assumes different many-core architectures. We implemented the prediction routers for each case study by using a 45 nm CMOS process, and evaluated them in terms of the prediction hit rate, zero-load Latency, hardware amount, and energy consumption. A typical prediction router with two or three predictors shows that although the area and energy are increased by 4.8-12.0 percent and 5.3 percent, respectively, up to 89.8 percent of the prediction hit rate is achieved in real applications, which provides favorable trade-offs between modest hardware/energy overheads and significant Latency saving.
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Prediction router: Yet another low Latency on-chip router architecture
Proceedings - International Symposium on High-Performance Computer Architecture, 2009Co-Authors: Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, Tsutomu YoshinagaAbstract:Network-on-Chips (NoCs) are quite Latency sensitive, since their Communication Latency strongly affects the application performance on recent many-core architectures. To reduce the Communication Latency, we propose a low-Latency router architecture that predicts an output channel being used by the next packet transfer and speculatively completes the switch arbitration. In the prediction routers, incoming packets are transferred without waiting the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing the Communication Latency is the hit rates of prediction algorithms, which vary from the network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-Latency routers that speculatively skip one or more pipeline stages use a bypass datapath for specific packet transfers (e.g., packets moving on the same dimension), our prediction router predictively forwards packets based on a prediction algorithm selected from several candidates in response to the network environments. In this paper, we analyze the prediction hit rates of six prediction algorithms on meshes, tori, and fat trees. Then we provide three case studies, each of which assumes different many-core architecture. We have implemented a prediction router for each case study by using a 65 nm CMOS process, and evaluated them in terms of the prediction hit rate, zero load Latency, hardware amount, and energy consumption. The results show that although the area and energy are increased by 6.4-15.9% and 8.0-9.5% respectively, up to 89.8% of the prediction hit rate is achieved in real applications, which provide favorable trade-offs between the modest hardware/energy overheads and the Latency saving.
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Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs
IEEE Transactions on Parallel and Distributed Systems, 2007Co-Authors: Konosuke Watanabe, Tomohiro Otsuka, Noboru Tanabe, Tomohiro Kudoh, Junji Yamamoto, Junichiro Tsuchiya, Hiroaki Nishi, Hideharu AmanoAbstract:In this paper, “Martini,” a network interface controller chip for our original network called RHiNET is described. Martini is designed to provide high-bandwidth and low-Latency Communication with small overhead. To obtain high performance Communication, protected user-level zero-copy RDMA Communication functions are completely implemented by a hardwired logic. Also, to reduce the Communication Latency efficiently, we have proposed PIO-based Communication mechanisms called “On-the-fly (OTF)” and have implemented them on Martini. The evaluation results show that Martini connected to a 64bit/66MHz PCI-bus achieves 470MByte/s maximum bidirectional bandwidth and 1.74 μsec minimum Latency on host-to-host memory copying.
Tsutomu Yoshinaga - One of the best experts on this subject based on the ideXlab platform.
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Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors
IEEE Transactions on Computers, 2011Co-Authors: Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, Tsutomu YoshinagaAbstract:Multi and many-core applications are sensitive to interprocessor Communication latencies, suggesting the need for low-Latency on-chip networks. We propose a low-Latency router architecture that predicts the output channel to be used by the next packet transfer and speculatively completes the switch arbitration to reduce Communication Latency. The packets coming into the prediction routers are transferred without waiting for the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing Communication Latency is the hit rates of the prediction algorithms, which vary based on network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-Latency routers that skip one or more pipeline stages use a bypass data path that is based on a static or single bypassing policy (e.g., accelerating the packets moving in the same dimension), our prediction router architecture predictively forwards packets based on the prediction algorithm selected from among several candidates in response to the network environment. We analyze the prediction hit rates of five prediction algorithms on meshes, tori, fat trees, and Spidergons. Then, we present four case studies, each of which assumes different many-core architectures. We implemented the prediction routers for each case study by using a 45 nm CMOS process, and evaluated them in terms of the prediction hit rate, zero-load Latency, hardware amount, and energy consumption. A typical prediction router with two or three predictors shows that although the area and energy are increased by 4.8-12.0 percent and 5.3 percent, respectively, up to 89.8 percent of the prediction hit rate is achieved in real applications, which provides favorable trade-offs between modest hardware/energy overheads and significant Latency saving.
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Prediction router: Yet another low Latency on-chip router architecture
Proceedings - International Symposium on High-Performance Computer Architecture, 2009Co-Authors: Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, Tsutomu YoshinagaAbstract:Network-on-Chips (NoCs) are quite Latency sensitive, since their Communication Latency strongly affects the application performance on recent many-core architectures. To reduce the Communication Latency, we propose a low-Latency router architecture that predicts an output channel being used by the next packet transfer and speculatively completes the switch arbitration. In the prediction routers, incoming packets are transferred without waiting the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing the Communication Latency is the hit rates of prediction algorithms, which vary from the network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-Latency routers that speculatively skip one or more pipeline stages use a bypass datapath for specific packet transfers (e.g., packets moving on the same dimension), our prediction router predictively forwards packets based on a prediction algorithm selected from several candidates in response to the network environments. In this paper, we analyze the prediction hit rates of six prediction algorithms on meshes, tori, and fat trees. Then we provide three case studies, each of which assumes different many-core architecture. We have implemented a prediction router for each case study by using a 65 nm CMOS process, and evaluated them in terms of the prediction hit rate, zero load Latency, hardware amount, and energy consumption. The results show that although the area and energy are increased by 6.4-15.9% and 8.0-9.5% respectively, up to 89.8% of the prediction hit rate is achieved in real applications, which provide favorable trade-offs between the modest hardware/energy overheads and the Latency saving.
N J Dimopoulos - One of the best experts on this subject based on the ideXlab platform.
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Communication Latency hiding in reconfigurable message passing environments quantitative studies
2002Co-Authors: Ahmad Afsahi, N J DimopoulosAbstract:Communications overhead is one of the most important factors affecting performance in message-passing multicomputers. We present evidence that there exists Communications locality, and that this locality is “structured”. We propose a number of heuristics that can be used to “predict” the target of subsequent Communication requests. Communication Latency is hidden through reconfiguring the network concurrently to the computation. Quantitative results obtained from standard parallel benchmarks run on IBM SP systems are also presented.
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design and evaluation of Communication Latency hiding reduction techniques for message passing environments
2000Co-Authors: N J Dimopoulos, Ahmad AfsahiAbstract:With the availability of fast microprocessors and small-scale multiprocessors, internode Communication has become an increasingly important factor that limits the performance of parallel computers. Essentially, message-passing parallel computers require extremely short Communication Latency such that message transmissions have minimal impact on the overall computation time. This thesis concentrates on issues regarding hardware Communication Latency in single-hop reconfigurable networks, and software Communication Latency regardless of the type of network. The first contribution of this thesis is the design and evaluation of two different categories of prediction techniques for message-passing systems. This thesis utilizes the Communications locality property of message-passing parallel applications to devise a number of heuristics that can be used to predict the target of subsequent Communication requests, and to predict the next consumable message at the receiving ends of Communications. Specifically, I propose two sets of predictors: Cycle-based predictors, which are purely dynamic predictors, and Tag-based predictors, which are static/dynamic predictors. The performance of the proposed predictors, specially Better-cycle2 and Tag-bettercycle2, are very well on the application benchmarks studied in this thesis. The proposed predictors could be easily implemented on the network interface due to their simple algorithms and low memory requirements. As the second contribution of this thesis, I show that majority of reconfiguration delays in single-hop reconfigurable networks can be hidden by using one of the proposed high hit ratio predictors. The proposed predictors can be used in establishing a Communication pathway between a source and a destination in such networks before this pathway is to be used. This thesis' third contribution is the analysis of a broadcasting algorithm that utilizes Latency hiding and reconfiguration in the network to speed the broadcasting operation. The analysis brings up closed formulations that yields the termination time of the algorithms. The thesis' fourth contribution is a new total exchange algorithm in single-hop reconfigurable networks. I conjecture that this algorithm ensures a better termination time than what can be achieved by either of the direct, and standard exchange algorithms. The fifth contribution of this thesis is the use and evaluation of the proposed predictors to predict the next consumable message at the receiving ends of Communications. This thesis contributes by claiming that these message predictors can be efficiently used to drain the network and cache the incoming messages even if the corresponding receive calls have not been posted yet. This way, there is no need to copy the early arriving messages into a temporary buffer. The performance of the proposed predictors, Single-cycle, Tag-cycle2 and Tag-bettercycle2, on the parallel applications are quite promising and suggest that prediction has the potential to eliminate most of the remaining message copies.
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hiding Communication Latency in reconfigurable message passing environments
International Parallel Processing Symposium, 1999Co-Authors: Ahmad Afsahi, N J DimopoulosAbstract:Communication overhead is one of the most important factors affecting the performance of message passing multicomputers. We present evidence (through the analysis of several parallel benchmarks) that there exists Communications locality, and that this locality is "structured". We have devised a number of heuristics that can "predict" the target of subsequent Communication requests. This technique, can be applied to reconfigurable interconnects to hide the Communications Latency by reconfiguring the interconnect concurrently to the computation. By comparing the inter-Communication computation times of a number of parallel benchmarks with some specific reconfiguration times, we argue that the computation interval can be used to hide the concurrent reconfiguration of the interconnect, and present the performance enhancements of the proposed heuristics.
Kaibin Huang - One of the best experts on this subject based on the ideXlab platform.
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broadband analog aggregation for low Latency federated edge learning
IEEE Transactions on Wireless Communications, 2020Co-Authors: Guangxu Zhu, Yong Wang, Kaibin HuangAbstract:To leverage rich data distributed at the network edge, a new machine-learning paradigm, called edge learning, has emerged where learning algorithms are deployed at the edge for providing intelligent services to mobile users. While computing speeds are advancing rapidly, the Communication Latency is becoming the bottleneck of fast edge learning. To address this issue, this work is focused on designing a low-Latency multi-access scheme for edge learning. To this end, we consider a popular privacy-preserving framework, federated edge learning (FEEL), where a global AI-model at an edge-server is updated by aggregating (averaging) local models trained at edge devices. It is proposed that the updates simultaneously transmitted by devices over broadband channels should be analog aggregated “over-the-air” by exploiting the waveform-superposition property of a multi-access channel. Such broadband analog aggregation (BAA) results in dramatical Communication-Latency reduction compared with the conventional orthogonal access (i.e., OFDMA). In this work, the effects of BAA on learning performance are quantified targeting a single-cell random network. First, we derive two tradeoffs between Communication-and-learning metrics, which are useful for network planning and optimization. The power control (“truncated channel inversion”) required for BAA results in a tradeoff between the update-reliability [as measured by the receive signal-to-noise ratio (SNR)] and the expected update-truncation ratio. Consider the scheduling of cell-interior devices to constrain path loss. This gives rise to the other tradeoff between the receive SNR and fraction of data exploited in learning. Next, the Latency-reduction ratio of the proposed BAA with respect to the traditional OFDMA scheme is proved to scale almost linearly with the device population. Experiments based on a neural network and a real dataset are conducted for corroborating the theoretical results.
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wireless networks for mobile edge computing spatial modeling and Latency analysis
IEEE Transactions on Wireless Communications, 2018Co-Authors: Kaifeng Han, Kaibin HuangAbstract:Next-generation wireless networks will provide users ubiquitous low-Latency computing services using devices at the network edge, called mobile edge computing (MEC). The key operation of MEC is to offload computation intensive tasks from users. Since each edge device comprises an access point (AP) and a computer server (CS), an MEC network can be decomposed as a radio access network cascaded with a CS network. Based on the architecture, we investigate network-constrained Latency performance, namely Communication Latency and computation Latency, under the constraints of radio-access connectivity and CS stability. To this end, a spatial random network is modeled featuring random node distribution, parallel computing, non-orthogonal multiple access, and random computation-task generation. Given the model and the said network constraints, we derive the scaling laws of Communication Latency and computation Latency with respect to network-load parameters (density of mobiles and their task-generation rates) and network-resource parameters (bandwidth, density of APs/CSs, and CS computation rate). Essentially, the analysis involves the interplay of the theories of stochastic geometry, queueing, and parallel computing. Combining the derived scaling laws quantifies the tradeoffs between the latencies, network connectivity, and network stability. The results provide useful guidelines for MEC-network provisioning and planning by avoiding either of the cascaded radio access network or CS network being a performance bottleneck.
Hiroki Matsutani - One of the best experts on this subject based on the ideXlab platform.
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Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors
IEEE Transactions on Computers, 2011Co-Authors: Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, Tsutomu YoshinagaAbstract:Multi and many-core applications are sensitive to interprocessor Communication latencies, suggesting the need for low-Latency on-chip networks. We propose a low-Latency router architecture that predicts the output channel to be used by the next packet transfer and speculatively completes the switch arbitration to reduce Communication Latency. The packets coming into the prediction routers are transferred without waiting for the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing Communication Latency is the hit rates of the prediction algorithms, which vary based on network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-Latency routers that skip one or more pipeline stages use a bypass data path that is based on a static or single bypassing policy (e.g., accelerating the packets moving in the same dimension), our prediction router architecture predictively forwards packets based on the prediction algorithm selected from among several candidates in response to the network environment. We analyze the prediction hit rates of five prediction algorithms on meshes, tori, fat trees, and Spidergons. Then, we present four case studies, each of which assumes different many-core architectures. We implemented the prediction routers for each case study by using a 45 nm CMOS process, and evaluated them in terms of the prediction hit rate, zero-load Latency, hardware amount, and energy consumption. A typical prediction router with two or three predictors shows that although the area and energy are increased by 4.8-12.0 percent and 5.3 percent, respectively, up to 89.8 percent of the prediction hit rate is achieved in real applications, which provides favorable trade-offs between modest hardware/energy overheads and significant Latency saving.
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Prediction router: Yet another low Latency on-chip router architecture
Proceedings - International Symposium on High-Performance Computer Architecture, 2009Co-Authors: Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi, Tsutomu YoshinagaAbstract:Network-on-Chips (NoCs) are quite Latency sensitive, since their Communication Latency strongly affects the application performance on recent many-core architectures. To reduce the Communication Latency, we propose a low-Latency router architecture that predicts an output channel being used by the next packet transfer and speculatively completes the switch arbitration. In the prediction routers, incoming packets are transferred without waiting the routing computation and switch arbitration if the prediction hits. Thus, the primary concern for reducing the Communication Latency is the hit rates of prediction algorithms, which vary from the network environments, such as the network topology, routing algorithm, and traffic pattern. Although typical low-Latency routers that speculatively skip one or more pipeline stages use a bypass datapath for specific packet transfers (e.g., packets moving on the same dimension), our prediction router predictively forwards packets based on a prediction algorithm selected from several candidates in response to the network environments. In this paper, we analyze the prediction hit rates of six prediction algorithms on meshes, tori, and fat trees. Then we provide three case studies, each of which assumes different many-core architecture. We have implemented a prediction router for each case study by using a 65 nm CMOS process, and evaluated them in terms of the prediction hit rate, zero load Latency, hardware amount, and energy consumption. The results show that although the area and energy are increased by 6.4-15.9% and 8.0-9.5% respectively, up to 89.8% of the prediction hit rate is achieved in real applications, which provide favorable trade-offs between the modest hardware/energy overheads and the Latency saving.