The Experts below are selected from a list of 54 Experts worldwide ranked by ideXlab platform
Laurence E Turner - One of the best experts on this subject based on the ideXlab platform.
-
bit serial digital filter implementation using a custom c Compiler
Asia Pacific Conference on Circuits and Systems, 2006Co-Authors: Dan Cyca, Laurence E TurnerAbstract:Bit-serial arithmetic offers the potential for more compact designs and increased levels of functional parallelism in comparison to bit-parallel arithmetic. While these advantages come at the expense of decreased throughput, there are areas of digital signal processing where the trade-off is desirable. Unfortunately, designers often overlook bit-serial arithmetic, partly due to a lack of design tools. This paper describes the design and implementation of a Compiler which generates bit-serial designs from a high-level language based on C. The Compiler targets a synthesizable VHDL bit-serial library, relying on a conventional VHDL backend for placement and routing. To exploit the relative low hardware cost of bit-serial operations, the Compiler employs techniques developed for conventional optimizing Compilers to extract fine-grained parallelism from high-level algorithms. Working from a high-level description of an algorithm, a designer can generate different design implementations from a single version of the source, using a parameterizable system word length, or by specifying a Compiler Option to trade-off latency for reduced parallelism, and therefore reduced hardware cost.
-
APCCAS - Bit-Serial Digital Filter Implementation using a Custom C Compiler
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006Co-Authors: Dan Cyca, Laurence E TurnerAbstract:Bit-serial arithmetic offers the potential for more compact designs and increased levels of functional parallelism in comparison to bit-parallel arithmetic. While these advantages come at the expense of decreased throughput, there are areas of digital signal processing where the trade-off is desirable. Unfortunately, designers often overlook bit-serial arithmetic, partly due to a lack of design tools. This paper describes the design and implementation of a Compiler which generates bit-serial designs from a high-level language based on C. The Compiler targets a synthesizable VHDL bit-serial library, relying on a conventional VHDL backend for placement and routing. To exploit the relative low hardware cost of bit-serial operations, the Compiler employs techniques developed for conventional optimizing Compilers to extract fine-grained parallelism from high-level algorithms. Working from a high-level description of an algorithm, a designer can generate different design implementations from a single version of the source, using a parameterizable system word length, or by specifying a Compiler Option to trade-off latency for reduced parallelism, and therefore reduced hardware cost.
Dan Cyca - One of the best experts on this subject based on the ideXlab platform.
-
bit serial digital filter implementation using a custom c Compiler
Asia Pacific Conference on Circuits and Systems, 2006Co-Authors: Dan Cyca, Laurence E TurnerAbstract:Bit-serial arithmetic offers the potential for more compact designs and increased levels of functional parallelism in comparison to bit-parallel arithmetic. While these advantages come at the expense of decreased throughput, there are areas of digital signal processing where the trade-off is desirable. Unfortunately, designers often overlook bit-serial arithmetic, partly due to a lack of design tools. This paper describes the design and implementation of a Compiler which generates bit-serial designs from a high-level language based on C. The Compiler targets a synthesizable VHDL bit-serial library, relying on a conventional VHDL backend for placement and routing. To exploit the relative low hardware cost of bit-serial operations, the Compiler employs techniques developed for conventional optimizing Compilers to extract fine-grained parallelism from high-level algorithms. Working from a high-level description of an algorithm, a designer can generate different design implementations from a single version of the source, using a parameterizable system word length, or by specifying a Compiler Option to trade-off latency for reduced parallelism, and therefore reduced hardware cost.
-
APCCAS - Bit-Serial Digital Filter Implementation using a Custom C Compiler
APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006Co-Authors: Dan Cyca, Laurence E TurnerAbstract:Bit-serial arithmetic offers the potential for more compact designs and increased levels of functional parallelism in comparison to bit-parallel arithmetic. While these advantages come at the expense of decreased throughput, there are areas of digital signal processing where the trade-off is desirable. Unfortunately, designers often overlook bit-serial arithmetic, partly due to a lack of design tools. This paper describes the design and implementation of a Compiler which generates bit-serial designs from a high-level language based on C. The Compiler targets a synthesizable VHDL bit-serial library, relying on a conventional VHDL backend for placement and routing. To exploit the relative low hardware cost of bit-serial operations, the Compiler employs techniques developed for conventional optimizing Compilers to extract fine-grained parallelism from high-level algorithms. Working from a high-level description of an algorithm, a designer can generate different design implementations from a single version of the source, using a parameterizable system word length, or by specifying a Compiler Option to trade-off latency for reduced parallelism, and therefore reduced hardware cost.
Eunjung Park - One of the best experts on this subject based on the ideXlab platform.
-
methodology of dynamic Compiler Option selection based on static program analysis implementation and evaluation
2007Co-Authors: Eunjung ParkAbstract:When we develop applications, it is important to write optimized code so that we can achieve good performance. However, the proper use of Compiler optimization Options is essential because obtaining the maximum possible performance by writing only optimized code (without Compiler’s help) is very difficult, if not impossible. Current Compilers possess a myriad of Options to optimize the application. Nevertheless, they provide a subset of Options called the standard optimization Options, which will provide safe optimization and give a reasonable optimized code. We can use the standard optimization Options; however, they are not always an optimal solution for all applications. Therefore, we should carefully choose the set of Options if we need additional performance improvement. This research area has three main challenges: (1) Due to the number of optimization Options in a Compiler, finding the optimal set of Options for a target program by brute force or any other exhaustive method is not simple. (2) Although we find the best set for the application, the Compiler will apply this set of Options to the whole program. Thus it is possible to lose some performance improvements because some Options may affect negatively specific parts and decrease the overall performance. (3) The absence of an automatic test platform gives more complexity in evaluation process so it is hard to test various benchmarks under different conditions. To resolve these problems, the methodology shown in [1] proposed how we identify performance sensitive code segments automatically. The key challenge in this methodology is how to automatically identify a special code segments to which customized set of optimization Options could be applied [1]. To address this
Wael Farag - One of the best experts on this subject based on the ideXlab platform.
-
Automatic selection of Compiler Options using genetic techniques for embedded software design
2013 IEEE 14th International Symposium on Computational Intelligence and Informatics (CINTI), 2013Co-Authors: Mena Nagiub, Wael FaragAbstract:ROM size and CPU load are considered as critical resources for the software design process of the embedded software. Thus it is necessary to produce software that follows specific ROM and CPU load requirements. Compiler Options play major role in the optimization of code size and CPU load of the software. Selection of the best Compiler Option-set that provides the required code size and CPU load is a challenging process due to the wide range of Options provided by modern Compilers. In this paper we are providing a new technique that enables the designers to select automatically the best Compiler Options set that matches their design requirements based on genetic techniques. We have also added a new genetics operator called pass-over operator to enhance the chromosomes selection for the next generation.
Jinpeng Zhang - One of the best experts on this subject based on the ideXlab platform.
-
Parallel computation of Doppler spectrum from dynamic sea surfaces at microwave bands
High-Performance Computing in Geoscience and Remote Sensing VIII, 2018Co-Authors: Longxiang Linghu, Jiaji Wu, Zhensen Wu, Jinpeng ZhangAbstract:The Doppler spectrum of the electromagnetic (EM) scattering field from the two-dimensional dynamic sea surface is calculated based on the composite scattering model. The two-dimensional dynamic sea surfaces are generally simulated as a superposition of large-scale gravity waves and small-scale capillary ripples. On this basis, the Doppler spectrum of the EM scattering field from the two-dimensional dynamic sea surface can be calculated based on the composite scattering model, which takes both the quasi-specular scattering and Bragg scattering mechanism into account. However, due to the high resolution and real-time dynamic complexity of the dynamic sea surfaces, the calculation of the Doppler spectrum will be computationally expensive and very time-consuming. In this paper, a GPU-based algorithm of Doppler spectrum was proposed by utilizing the Tesla K80 GPUs with diverse CUDA optimization techniques. The GPU-based Doppler spectrum implementation includes five optimization strategies: first, the temporary arrays are utilized to reduce the repeat float-points operations in the loop; then the device memory was effectively exploited to reduce the data transfer time between the CPU and GPU; the fast math Compiler Option was also utilized to further improve the computation performance of the Doppler spectrum calculation; finally the data transfer time between the device and host memories can be effectively hide by using the asynchronous data transfer (ADT). Compared to the CPU serial program executed on Intel(R) Core(TM) i5-3450 CPU, the GPU-based Doppler spectrum implementation can achieve a significant speedup of1200× .