The Experts below are selected from a list of 19947 Experts worldwide ranked by ideXlab platform
Rui P Martins - One of the best experts on this subject based on the ideXlab platform.
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A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS
2016Co-Authors: Zhicheng Lin, Puiin Mak, Senior Member, Rui P MartinsAbstract:LNA-I/Q-mixer (Blixer) and a baseband (BB) hybrid filter in one cell is fabricated in 65 nm CMOS. Without any external components, wideband input matching and passive pre-gain are concurrently achieved via co-optimizing an integrated low-Q network with a balun-LNA. The latter also features active-gain boosting and partial-noise canceling to enhance the gain and noise figure (NF). Above the balun-LNA are I/Q double-balanced mixers driven by a 4-phase 25 % LO for downconversion and gain-phase balancing. The generated BB currents are immediately filtered by an IF-noise-shaping current-mode Biquad and a Complex-Pole load, offering first-order image rejection and third-order channel selection directly atop the Blixer. Together with other BB and LO circuitries, the receiver measures 8.5 dB NF, 57 dB gain and 6-dBm IIP3 at 1.7 mW power and 0.24 mm die size. The S-bandwidth ( 10 dB) covers 2.25 to 3.55 GHz being ro-bust to packaging variations. Most performance metrics compare favorably with the state-of-the-art. Index Terms—Balun low-noise amplifier (Balun-LNA), CMOS, current reuse, hybrid filter, local oscillator (LO), mixer, noise figure (NF), noise-canceling, noise-shaping, output balancing, polyphase filter (PPF), RC-CR network, receiver, voltage-con-trolled oscillator (VCO), wireless, ZigBee. I
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a 0 02 mm 2 59 2 db sfdr 4th order sc lpf with 0 5 to 10 mhz bandwidth scalability exploiting a recycling sc buffer biquad
IEEE Journal of Solid-state Circuits, 2015Co-Authors: Yaohua Zhao, Puiin Mak, Rui P Martins, Franco MalobertiAbstract:This paper reports a switched-capacitor (SC)-buffer Biquad that can be recycled efficiently as an ultra-compact low-pass filter (LPF) in nanoscale CMOS. It incorporates only passive-SC networks and open-loop unity-gain buffers; both are friendlier to technology downscaling than most conventional Biquads that use high-gain amplifiers and closed-loop negative feedback. Complex-Pole pairs with independent Q factors are recursively realized in one clock period, while ensuring low crosstalk effect between the formations of each Pole. Nonlinearity and parasitic effects are inherently low due to no internal gain. The fabricated 65 nm CMOS prototype is a 1x-recycling SC-buffer Biquad that is equivalent to a 4th-order Butterworth LPF with 75% buffer utilization. It occupies a die size of only 0.02 mm $^{2}$ and exhibits 20x bandwidth tunability (0.5 to 10 MHz), linear with the clock rate. At 10 MHz bandwidth, the in-band IIP3 is +17.6 dBm and input-referred noise is 19.5 nV/ $\surd$ Hz; they correspond to 59.2 dB SFDR and 0.013 fJ figure-of-merit which are favorably comparable with the recent art. The 1 dB compression point $({\rm P}_{1{\rm dB}})$ conforms to the out-of-band blocker profile of the LTE standard at a 20 dB front-end gain.
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a 2 4 ghz zigbee receiver exploiting an rf to bb current reuse blixer hybrid filter topology in 65 nm cmos
IEEE Journal of Solid-state Circuits, 2014Co-Authors: Zhicheng Lin, Puiin Mak, Rui P MartinsAbstract:A 2.4 GHz ZigBee receiver unifying a balun-LNA-I/Q-mixer (Blixer) and a baseband (BB) hybrid filter in one cell is fabricated in 65 nm CMOS. Without any external components, wideband input matching and passive pre-gain are concurrently achieved via co-optimizing an integrated low-Q network with a balun-LNA. The latter also features active-gain boosting and partial-noise canceling to enhance the gain and noise figure (NF). Above the balun-LNA are I/Q double-balanced mixers driven by a 4-phase 25% LO for downconversion and gain-phase balancing. The generated BB currents are immediately filtered by an IF-noise-shaping current-mode Biquad and a Complex-Pole load, offering first-order image rejection and third-order channel selection directly atop the Blixer. Together with other BB and LO circuitries, the receiver measures 8.5 dB NF, 57 dB gain and $-$ 6-dBm IIP3 $_{{\rm out}\mathchar"702D{\rm band}}$ at 1.7 mW power and 0.24 mm $^{2}$ die size. The S $_{11}$ -bandwidth ( ${ 10 dB) covers 2.25 to 3.55 GHz being robust to packaging variations. Most performance metrics compare favorably with the state-of-the-art.
Puiin Mak - One of the best experts on this subject based on the ideXlab platform.
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A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS
2016Co-Authors: Zhicheng Lin, Puiin Mak, Senior Member, Rui P MartinsAbstract:LNA-I/Q-mixer (Blixer) and a baseband (BB) hybrid filter in one cell is fabricated in 65 nm CMOS. Without any external components, wideband input matching and passive pre-gain are concurrently achieved via co-optimizing an integrated low-Q network with a balun-LNA. The latter also features active-gain boosting and partial-noise canceling to enhance the gain and noise figure (NF). Above the balun-LNA are I/Q double-balanced mixers driven by a 4-phase 25 % LO for downconversion and gain-phase balancing. The generated BB currents are immediately filtered by an IF-noise-shaping current-mode Biquad and a Complex-Pole load, offering first-order image rejection and third-order channel selection directly atop the Blixer. Together with other BB and LO circuitries, the receiver measures 8.5 dB NF, 57 dB gain and 6-dBm IIP3 at 1.7 mW power and 0.24 mm die size. The S-bandwidth ( 10 dB) covers 2.25 to 3.55 GHz being ro-bust to packaging variations. Most performance metrics compare favorably with the state-of-the-art. Index Terms—Balun low-noise amplifier (Balun-LNA), CMOS, current reuse, hybrid filter, local oscillator (LO), mixer, noise figure (NF), noise-canceling, noise-shaping, output balancing, polyphase filter (PPF), RC-CR network, receiver, voltage-con-trolled oscillator (VCO), wireless, ZigBee. I
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a 0 02 mm 2 59 2 db sfdr 4th order sc lpf with 0 5 to 10 mhz bandwidth scalability exploiting a recycling sc buffer biquad
IEEE Journal of Solid-state Circuits, 2015Co-Authors: Yaohua Zhao, Puiin Mak, Rui P Martins, Franco MalobertiAbstract:This paper reports a switched-capacitor (SC)-buffer Biquad that can be recycled efficiently as an ultra-compact low-pass filter (LPF) in nanoscale CMOS. It incorporates only passive-SC networks and open-loop unity-gain buffers; both are friendlier to technology downscaling than most conventional Biquads that use high-gain amplifiers and closed-loop negative feedback. Complex-Pole pairs with independent Q factors are recursively realized in one clock period, while ensuring low crosstalk effect between the formations of each Pole. Nonlinearity and parasitic effects are inherently low due to no internal gain. The fabricated 65 nm CMOS prototype is a 1x-recycling SC-buffer Biquad that is equivalent to a 4th-order Butterworth LPF with 75% buffer utilization. It occupies a die size of only 0.02 mm $^{2}$ and exhibits 20x bandwidth tunability (0.5 to 10 MHz), linear with the clock rate. At 10 MHz bandwidth, the in-band IIP3 is +17.6 dBm and input-referred noise is 19.5 nV/ $\surd$ Hz; they correspond to 59.2 dB SFDR and 0.013 fJ figure-of-merit which are favorably comparable with the recent art. The 1 dB compression point $({\rm P}_{1{\rm dB}})$ conforms to the out-of-band blocker profile of the LTE standard at a 20 dB front-end gain.
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a 2 4 ghz zigbee receiver exploiting an rf to bb current reuse blixer hybrid filter topology in 65 nm cmos
IEEE Journal of Solid-state Circuits, 2014Co-Authors: Zhicheng Lin, Puiin Mak, Rui P MartinsAbstract:A 2.4 GHz ZigBee receiver unifying a balun-LNA-I/Q-mixer (Blixer) and a baseband (BB) hybrid filter in one cell is fabricated in 65 nm CMOS. Without any external components, wideband input matching and passive pre-gain are concurrently achieved via co-optimizing an integrated low-Q network with a balun-LNA. The latter also features active-gain boosting and partial-noise canceling to enhance the gain and noise figure (NF). Above the balun-LNA are I/Q double-balanced mixers driven by a 4-phase 25% LO for downconversion and gain-phase balancing. The generated BB currents are immediately filtered by an IF-noise-shaping current-mode Biquad and a Complex-Pole load, offering first-order image rejection and third-order channel selection directly atop the Blixer. Together with other BB and LO circuitries, the receiver measures 8.5 dB NF, 57 dB gain and $-$ 6-dBm IIP3 $_{{\rm out}\mathchar"702D{\rm band}}$ at 1.7 mW power and 0.24 mm $^{2}$ die size. The S $_{11}$ -bandwidth ( ${ 10 dB) covers 2.25 to 3.55 GHz being robust to packaging variations. Most performance metrics compare favorably with the state-of-the-art.
Stephen P Martin - One of the best experts on this subject based on the ideXlab platform.
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z boson Pole mass at two loop order in the pure overline ms scheme
Physical Review D, 2015Co-Authors: Stephen P MartinAbstract:I obtain the Complex Pole squared mass of the Z boson at full two-loop order in the Standard Model in the pure MS-bar renormalization scheme. The input parameters are the running gauge couplings, the top-quark Yukawa coupling, the Higgs self-coupling, and the vacuum expectation value that minimizes the Landau gauge effective potential. The effects of non-zero Goldstone boson mass are resummed. Within a reasonable range of renormalization scale choices, the scale dependence of the computed Pole mass is found to be comparable to the current experimental uncertainty, but the true theoretical error is likely somewhat larger.
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Pole mass of the w boson at two loop order in the pure overline ms scheme
Physical Review D, 2015Co-Authors: Stephen P MartinAbstract:I provide a calculation at full two-loop order of the Complex Pole squared mass of the W boson in the Standard Model in the pure MS-bar renormalization scheme, with Goldstone boson mass effects resummed. This approach is an alternative to earlier ones that use on-shell or hybrid renormalization schemes. The renormalization scale dependence of the real and imaginary parts of the resulting Pole mass are studied. Both deviate by about $\pm 4$ MeV from their median values as the renormalization scale is varied from 50 GeV to 200 GeV, but the theory error is likely larger. A surprising feature of this scheme is that the 2-loop QCD correction has a larger scale-dependence, but a smaller magnitude, than the 2-loop non-QCD correction, unless the renormalization scale is chosen very far from the top-quark mass.
Zhicheng Lin - One of the best experts on this subject based on the ideXlab platform.
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A 2.4 GHz ZigBee Receiver Exploiting an RF-to-BB-Current-Reuse Blixer + Hybrid Filter Topology in 65 nm CMOS
2016Co-Authors: Zhicheng Lin, Puiin Mak, Senior Member, Rui P MartinsAbstract:LNA-I/Q-mixer (Blixer) and a baseband (BB) hybrid filter in one cell is fabricated in 65 nm CMOS. Without any external components, wideband input matching and passive pre-gain are concurrently achieved via co-optimizing an integrated low-Q network with a balun-LNA. The latter also features active-gain boosting and partial-noise canceling to enhance the gain and noise figure (NF). Above the balun-LNA are I/Q double-balanced mixers driven by a 4-phase 25 % LO for downconversion and gain-phase balancing. The generated BB currents are immediately filtered by an IF-noise-shaping current-mode Biquad and a Complex-Pole load, offering first-order image rejection and third-order channel selection directly atop the Blixer. Together with other BB and LO circuitries, the receiver measures 8.5 dB NF, 57 dB gain and 6-dBm IIP3 at 1.7 mW power and 0.24 mm die size. The S-bandwidth ( 10 dB) covers 2.25 to 3.55 GHz being ro-bust to packaging variations. Most performance metrics compare favorably with the state-of-the-art. Index Terms—Balun low-noise amplifier (Balun-LNA), CMOS, current reuse, hybrid filter, local oscillator (LO), mixer, noise figure (NF), noise-canceling, noise-shaping, output balancing, polyphase filter (PPF), RC-CR network, receiver, voltage-con-trolled oscillator (VCO), wireless, ZigBee. I
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a 2 4 ghz zigbee receiver exploiting an rf to bb current reuse blixer hybrid filter topology in 65 nm cmos
IEEE Journal of Solid-state Circuits, 2014Co-Authors: Zhicheng Lin, Puiin Mak, Rui P MartinsAbstract:A 2.4 GHz ZigBee receiver unifying a balun-LNA-I/Q-mixer (Blixer) and a baseband (BB) hybrid filter in one cell is fabricated in 65 nm CMOS. Without any external components, wideband input matching and passive pre-gain are concurrently achieved via co-optimizing an integrated low-Q network with a balun-LNA. The latter also features active-gain boosting and partial-noise canceling to enhance the gain and noise figure (NF). Above the balun-LNA are I/Q double-balanced mixers driven by a 4-phase 25% LO for downconversion and gain-phase balancing. The generated BB currents are immediately filtered by an IF-noise-shaping current-mode Biquad and a Complex-Pole load, offering first-order image rejection and third-order channel selection directly atop the Blixer. Together with other BB and LO circuitries, the receiver measures 8.5 dB NF, 57 dB gain and $-$ 6-dBm IIP3 $_{{\rm out}\mathchar"702D{\rm band}}$ at 1.7 mW power and 0.24 mm $^{2}$ die size. The S $_{11}$ -bandwidth ( ${ 10 dB) covers 2.25 to 3.55 GHz being robust to packaging variations. Most performance metrics compare favorably with the state-of-the-art.
Winghung Ki - One of the best experts on this subject based on the ideXlab platform.
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a cascode miller compensated three stage amplifier with local impedance attenuation for optimized Complex Pole control
IEEE Journal of Solid-state Circuits, 2015Co-Authors: Winghung KiAbstract:This work presents a power- and area-efficient three-stage amplifier that is able to drive a large capacitive load. Removing the inner Miller capacitor and employing cascode Miller compensation in the outer compensation loop could extend the Complex-Pole frequency of a three-stage amplifier, but result in a high Q-factor. A local impedance attenuation block consisting of a series RC network is proposed to control the Complex Poles. This block attenuates the high-frequency resistance at the second-stage output and achieves an optimized tradeoff between the frequency and the Q-factor of the Complex Poles. As the low-frequency resistance remains unchanged, a high dc gain is maintained. Implemented in 0.13 $\mu$ m CMOS process, the proposed design occupies an area of 0.0032 mm 2 and consumes a quiescent current of 10.5 $\mu$ A. When driving a 560 pF capacitive load, it achieves a unity-gain frequency of 3.49 MHz, an average slew rate of 0.86 V/ $\mu$ s, and an average settling time of 0.9 $\mu$ s.