The Experts below are selected from a list of 25698 Experts worldwide ranked by ideXlab platform

Matthieu Arzel - One of the best experts on this subject based on the ideXlab platform.

  • ultra low energy mixed signal ic implementing encoded neural networks
    IEEE Transactions on Circuits and Systems, 2016
    Co-Authors: Benoit Larras, Cyril Lahuec, Fabrice Seguin, Matthieu Arzel
    Abstract:

    Encoded Neural Networks (ENNs) associate low-complexity algorithm with a storage capacity much larger than Hopfield Neural Networks (HNNs) for the same number of Nodes. Moreover, they have a lower density than HNNs in terms of connections, allowing a low-complexity circuit integration. The implementation of such a network requires low-complexity elements to take complete advantage of the assets of the model. This paper proposes an analog implementation of the ENNs. It is shown that this type of implementation is suitable for building network of thousands of Nodes. To validate the proposed implementation, a prototype ENN of 30 Computation Nodes is designed, fabricated and tested on-chip for the ST 65-nm 1-V supply complementary metal-oxide silicon (CMOS) process. The circuit shows decoding performance similar to that of the theoretical model, and decodes a message in 58 ns. Moreover, the entire network occupies a silicon area of 16470 $\mu\text{m}^{2}$ and consumes 145 $\mu\text{W}$ , yielding a measured energy consumption per synaptic event per Computation Node of 68 fJ.

Benoit Larras - One of the best experts on this subject based on the ideXlab platform.

  • ultra low energy mixed signal ic implementing encoded neural networks
    IEEE Transactions on Circuits and Systems, 2016
    Co-Authors: Benoit Larras, Cyril Lahuec, Fabrice Seguin, Matthieu Arzel
    Abstract:

    Encoded Neural Networks (ENNs) associate low-complexity algorithm with a storage capacity much larger than Hopfield Neural Networks (HNNs) for the same number of Nodes. Moreover, they have a lower density than HNNs in terms of connections, allowing a low-complexity circuit integration. The implementation of such a network requires low-complexity elements to take complete advantage of the assets of the model. This paper proposes an analog implementation of the ENNs. It is shown that this type of implementation is suitable for building network of thousands of Nodes. To validate the proposed implementation, a prototype ENN of 30 Computation Nodes is designed, fabricated and tested on-chip for the ST 65-nm 1-V supply complementary metal-oxide silicon (CMOS) process. The circuit shows decoding performance similar to that of the theoretical model, and decodes a message in 58 ns. Moreover, the entire network occupies a silicon area of 16470 $\mu\text{m}^{2}$ and consumes 145 $\mu\text{W}$ , yielding a measured energy consumption per synaptic event per Computation Node of 68 fJ.

Fabrice Seguin - One of the best experts on this subject based on the ideXlab platform.

  • ultra low energy mixed signal ic implementing encoded neural networks
    IEEE Transactions on Circuits and Systems, 2016
    Co-Authors: Benoit Larras, Cyril Lahuec, Fabrice Seguin, Matthieu Arzel
    Abstract:

    Encoded Neural Networks (ENNs) associate low-complexity algorithm with a storage capacity much larger than Hopfield Neural Networks (HNNs) for the same number of Nodes. Moreover, they have a lower density than HNNs in terms of connections, allowing a low-complexity circuit integration. The implementation of such a network requires low-complexity elements to take complete advantage of the assets of the model. This paper proposes an analog implementation of the ENNs. It is shown that this type of implementation is suitable for building network of thousands of Nodes. To validate the proposed implementation, a prototype ENN of 30 Computation Nodes is designed, fabricated and tested on-chip for the ST 65-nm 1-V supply complementary metal-oxide silicon (CMOS) process. The circuit shows decoding performance similar to that of the theoretical model, and decodes a message in 58 ns. Moreover, the entire network occupies a silicon area of 16470 $\mu\text{m}^{2}$ and consumes 145 $\mu\text{W}$ , yielding a measured energy consumption per synaptic event per Computation Node of 68 fJ.

Cyril Lahuec - One of the best experts on this subject based on the ideXlab platform.

  • ultra low energy mixed signal ic implementing encoded neural networks
    IEEE Transactions on Circuits and Systems, 2016
    Co-Authors: Benoit Larras, Cyril Lahuec, Fabrice Seguin, Matthieu Arzel
    Abstract:

    Encoded Neural Networks (ENNs) associate low-complexity algorithm with a storage capacity much larger than Hopfield Neural Networks (HNNs) for the same number of Nodes. Moreover, they have a lower density than HNNs in terms of connections, allowing a low-complexity circuit integration. The implementation of such a network requires low-complexity elements to take complete advantage of the assets of the model. This paper proposes an analog implementation of the ENNs. It is shown that this type of implementation is suitable for building network of thousands of Nodes. To validate the proposed implementation, a prototype ENN of 30 Computation Nodes is designed, fabricated and tested on-chip for the ST 65-nm 1-V supply complementary metal-oxide silicon (CMOS) process. The circuit shows decoding performance similar to that of the theoretical model, and decodes a message in 58 ns. Moreover, the entire network occupies a silicon area of 16470 $\mu\text{m}^{2}$ and consumes 145 $\mu\text{W}$ , yielding a measured energy consumption per synaptic event per Computation Node of 68 fJ.

Catthoor Francky - One of the best experts on this subject based on the ideXlab platform.

  • Enabling Resource-Aware Mapping of Spiking Neural Networks via Spatial Decomposition
    2020
    Co-Authors: Balaji Adarsha, Song Shihao, Das Anup, Krichmar Jeffrey, Dutt Nikil, Shackleford James, Kandasamy Nagarajan, Catthoor Francky
    Abstract:

    With growing model complexity, mapping Spiking Neural Network (SNN)-based applications to tile-based neuromorphic hardware is becoming increasingly challenging. This is because the synaptic storage resources on a tile, viz. a crossbar, can accommodate only a fixed number of pre-synaptic connections per post-synaptic neuron. For complex SNN models that have many pre-synaptic connections per neuron, some connections may need to be pruned after training to fit onto the tile resources, leading to a loss in model quality, e.g., accuracy. In this work, we propose a novel unrolling technique that decomposes a neuron function with many pre-synaptic connections into a sequence of homogeneous neural units, where each neural unit is a function Computation Node, with two pre-synaptic connections. This spatial decomposition technique significantly improves crossbar utilization and retains all pre-synaptic connections, resulting in no loss of the model quality derived from connection pruning. We integrate the proposed technique within an existing SNN mapping framework and evaluate it using machine learning applications on the DYNAP-SE state-of-the-art neuromorphic hardware. Our results demonstrate an average 60% lower crossbar requirement, 9x higher synapse utilization, 62% lower wasted energy on the hardware, and between 0.8% and 4.6% increase in model quality.Comment: Accepted for publication of IEEE Embedded Systems Letter