The Experts below are selected from a list of 264 Experts worldwide ranked by ideXlab platform
Peter W. Shor - One of the best experts on this subject based on the ideXlab platform.
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scheme for reducing decoherence in quantum Computer Memory
Physical Review A, 1995Co-Authors: Peter W. ShorAbstract:In the mid-1990s, theorists devised methods to preserve the integrity of quantum bits\char22{}techniques that may become the key to practical quantum computing on a large scale.
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Scheme for reducing decoherence in quantum Computer Memory
Physical Review A, 1995Co-Authors: Peter W. ShorAbstract:Recently, it was realized that use of the properties of quantum mechanics might speed up certain computations dramatically. Interest has since been growing in the area of quantum computation. One of the main difficulties of quantum computation is that decoherence destroys the information in a superposition of states contained in a quantum Computer, thus making long computations impossible. It is shown how to reduce the effects of decoherence for information stored in quantum Memory, assuming that the decoherence process acts independently on each of the bits stored in Memory. This involves the use of a quantum analog of error-correcting codes.
C. Silvano - One of the best experts on this subject based on the ideXlab platform.
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Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for Computer Memory systems
IEEE Transactions on Information Theory, 1995Co-Authors: L. Penzo, D. Sciuto, C. SilvanoAbstract:Three new techniques are proposed for constructing a class of codes that extends the protection provided by previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes. The proposed codes are systematic odd-weight-column SEC-DED-SBD codes providing also the correction of any odd number of erroneous bits per byte, where a byte represents a cluster of b bits of the codeword that are fed by the same Memory chip or card. These codes are useful for practical applications to enhance the reliability and the data integrity of byte-organized Computer Memory systems against transient, intermittent, and permanent failures. In particular they represent a good tradeoff between the overhead in terms of additional check bits and the reliability improvement, due to the capability to correct at least 50% of the multiple errors per byte.
T. Selker - One of the best experts on this subject based on the ideXlab platform.
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IEEE Visualization - Visualizing Computer Memory architectures
Proceedings of the First IEEE Conference on Visualization: Visualization `90, 1990Co-Authors: B. Alpern, L. Carter, T. SelkerAbstract:The authors describe a conceptual model, the Memory hierarchy framework, and a visual language for using the model. The model is more faithful to the structure of Computers than the Von Neumann and Turing models. It addresses the issues of data movement and exposes and unifies storage mechanisms such as cache, translation lookaside buffers, main Memory, and disks. The visual language presents the details of a Computer's Memory hierarchy in a concise drawing composed of rectangles and connecting segments. Using this framework, the authors improved the performance of a matrix multiplication algorithm by more than an order of magnitude. The framework gives insight into Computer architecture and performance bottlenecks by making effective use of human visual abilities. >
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Visualizing Computer Memory architectures
Proceedings of the First IEEE Conference on Visualization: Visualization `90, 1990Co-Authors: B. Alpern, L. Carter, T. SelkerAbstract:The authors describe a conceptual model, the Memory hierarchy framework, and a visual language for using the model. The model is more faithful to the structure of Computers than the Von Neumann and Turing models. It addresses the issues of data movement and exposes and unifies storage mechanisms such as cache, translation lookaside buffers, main Memory, and disks. The visual language presents the details of a Computer's Memory hierarchy in a concise drawing composed of rectangles and connecting segments. Using this framework, the authors improved the performance of a matrix multiplication algorithm by more than an order of magnitude. The framework gives insight into Computer architecture and performance bottlenecks by making effective use of human visual abilities.
L. Penzo - One of the best experts on this subject based on the ideXlab platform.
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Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for Computer Memory systems
IEEE Transactions on Information Theory, 1995Co-Authors: L. Penzo, D. Sciuto, C. SilvanoAbstract:Three new techniques are proposed for constructing a class of codes that extends the protection provided by previous single error correcting (SEC)-double error detecting (DED)-single byte error detecting (SBD) codes. The proposed codes are systematic odd-weight-column SEC-DED-SBD codes providing also the correction of any odd number of erroneous bits per byte, where a byte represents a cluster of b bits of the codeword that are fed by the same Memory chip or card. These codes are useful for practical applications to enhance the reliability and the data integrity of byte-organized Computer Memory systems against transient, intermittent, and permanent failures. In particular they represent a good tradeoff between the overhead in terms of additional check bits and the reliability improvement, due to the capability to correct at least 50% of the multiple errors per byte.
John Mcbrewster - One of the best experts on this subject based on the ideXlab platform.
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Magnetic core Memory: Random access, Computer Memory, Ceramic, Magnetic field, Polarity (physics), Core dump, Delay line Memory, Twistor Memory, Bubble ... Random Access Memory, Ferroelectric RAM
2009Co-Authors: Frederic P. Miller, Agnes F. Vandome, John McbrewsterAbstract:Magnetic core Memory, also known as Forrester Memory or ferrite-core Memory, is an early form of random access Computer Memory. It uses small magnetic ceramic rings, the cores, through which wires are threaded to store information via the polarity of the magnetic field they contain. Such Memory is often just called core Memory, or, informally, core. Although Computer Memory long ago moved to silicon chips, Memory is still occasionally called "core". This is most obvious in the naming of the core dump, which refers to the contents of Memory recorded at the time of a program error.
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Binary prefix: Binary prefix, Bit, Byte, Computer Memory, SI prefix, Serial communication, Transmission medium, National Institute of Standards and Technology, ... Electrotechnical Commission, IEC 60027
2009Co-Authors: Frederic P. Miller, Agnes F. Vandome, John McbrewsterAbstract:In computing, a binary prefix is a set of letters that precede a unit of digital quantity (bit and byte) to indicate multiplication by a power of two. In certain contexts in computing, such as Computer Memory size, the units bit and byte have traditionally been reported in multiples of powers of two. The term binary prefix is intended to differentiate usage of the multiple's names and symbols (for example, kilo or k) from the SI prefixes, which are always decimal (power of 10) multiples. The first few binary multipliers, e.g., 1024 (210), 1048576 (220), are close in value to SI prefixes, such as kilo (1000 = 103) and mega (1000000 = 106), respectively. Therefore it became common practice amongst Computer professionals to use these prefixes for the binary multiples, for example, to use the symbol M (mega) to mean 1048576 instead of 1000000. However, when used with SI units and in some other contexts, these prefixes retained their decimal meanings. Certain disciplines of computing have always used these prefixes as decimal multipliers, for example, when specifying quantities of bits transmitted on a serial transmission medium.
