The Experts below are selected from a list of 198 Experts worldwide ranked by ideXlab platform
Pierre Michaud - One of the best experts on this subject based on the ideXlab platform.
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An Alternative TAGE-like Conditional Branch Predictor
ACM Transactions on Architecture and Code Optimization, 2018Co-Authors: Pierre MichaudAbstract:TAGE is one of the most accurate Conditional Branch predictors known today. However, TAGE does not exploit its input information perfectly, as it is possible to obtain significant prediction accuracy improvements by complementing TAGE with a statistical corrector using the same input information. This article proposes an alternative TAGE-like predictor making statistical correction practically superfluous.
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pushing the Branch predictability limits with the multi potage sc predictor
4th JILP Workshop on Computer Architecture Competitions (JWAC-4): Championship Branch Prediction (CBP-4), 2014Co-Authors: Pierre Michaud, André SeznecAbstract:This paper describes the Conditional Branch predictor that the authors submitted to the unlimited-size track of the 4th Championship Branch Prediction. The multi-poTAGE+SC predictor which we submit combines the multi-poTAGE and TAGE-SC predictors that were submitted separately to CBP-4 by the first and second authors respectively. Both multi-poTAGE and TAGE-SC are based on the TAGE predictor. We combine them by replacing the TAGE component in TAGE-SC with the multi-poTAGE.
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trading conflict and capacity aliasing in Conditional Branch predictors
International Symposium on Computer Architecture, 1997Co-Authors: Pierre Michaud, André Seznec, Richard UhligAbstract:As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate Branch prediction. Because hardware resources for Branch-predictor tables are invariably limited, it is not possible to hold all relevant Branch history for all active Branches at the same time, especially for large workloads consisting of multiple processes and operating-system code. The problem that results, commonly referred to as aliasing in the Branch-predictor tables, is in many ways similar to the misses that occur in finite-sized hardware caches.In this paper we propose a new classification for Branch aliasing based on the three-Cs model for caches, and show that conflict aliasing is a significant source of mispredictions. Unfortunately, the obvious method for removing conflicts --- adding tags and associativity to the predictor tables --- is not a cost-effective solution.To address this problem, we propose the skewed Branch predictor, a multi-bank, tag-less Branch predictor, designed specifically to reduce the impact of conflict aliasing. Through both analytical and simulation models, we show that the skewed Branch predictor removes a substantial portion of conflict aliasing by introducing redundancy to the Branch-predictor tables. Although this redundancy increases capacity aliasing compared to a standard one-bank structure of comparable size, our simulations show that the reduction in conflict aliasing overcomes this effect to yield a gain in prediction accuracy. Alternatively, we show that a skewed organization can achieve the same prediction accuracy as a standard one-bank organization but with half the storage requirements.
André Seznec - One of the best experts on this subject based on the ideXlab platform.
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pushing the Branch predictability limits with the multi potage sc predictor
4th JILP Workshop on Computer Architecture Competitions (JWAC-4): Championship Branch Prediction (CBP-4), 2014Co-Authors: Pierre Michaud, André SeznecAbstract:This paper describes the Conditional Branch predictor that the authors submitted to the unlimited-size track of the 4th Championship Branch Prediction. The multi-poTAGE+SC predictor which we submit combines the multi-poTAGE and TAGE-SC predictors that were submitted separately to CBP-4 by the first and second authors respectively. Both multi-poTAGE and TAGE-SC are based on the TAGE predictor. We combine them by replacing the TAGE component in TAGE-SC with the multi-poTAGE.
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design tradeoffs for the alpha ev8 Conditional Branch predictor
International Symposium on Computer Architecture, 2002Co-Authors: André Seznec, Stephen Felix, Venkata Krishnan, Yiannakis SazeidesAbstract:This paper presents the Alpha EV8 Conditional Branch predictor The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressive 8-wide issue out-of-order superscalar microarchitecture featuring a very deep pipeline and simultaneous multithreading. Performance of such a processor is highly dependent on the accuracy of its Branch predictor and consequently a very large silicon area was devoted to Branch prediction on EV8. The Alpha EV8 Branch predictor relies on global history and features a total of 352 Kbits.The focus of this paper is on the different trade-offs performed to overcome various implementation constraints for the EV8 Branch predictor. One such instance is the pipelining of the predictor on two cycles to facilitate the prediction of up to 16 Branches per cycle from any two dynamically successive, 8 instruction fetch blocks. This resulted in the use of three fetch-block old compressed Branch history information for accesing the predictor. Implementation constraints also restricted the composition of the index functions for the predictor and forced the usage of only single-ported memory cells.Nevertheless, we show that the Alpha EV8 Branch predictor achieves prediction accuracy in the same range as the state-of-the-art academic global history Branch predictors that do not consider implementation constraints in great detail.
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trading conflict and capacity aliasing in Conditional Branch predictors
International Symposium on Computer Architecture, 1997Co-Authors: Pierre Michaud, André Seznec, Richard UhligAbstract:As modern microprocessors employ deeper pipelines and issue multiple instructions per cycle, they are becoming increasingly dependent on accurate Branch prediction. Because hardware resources for Branch-predictor tables are invariably limited, it is not possible to hold all relevant Branch history for all active Branches at the same time, especially for large workloads consisting of multiple processes and operating-system code. The problem that results, commonly referred to as aliasing in the Branch-predictor tables, is in many ways similar to the misses that occur in finite-sized hardware caches.In this paper we propose a new classification for Branch aliasing based on the three-Cs model for caches, and show that conflict aliasing is a significant source of mispredictions. Unfortunately, the obvious method for removing conflicts --- adding tags and associativity to the predictor tables --- is not a cost-effective solution.To address this problem, we propose the skewed Branch predictor, a multi-bank, tag-less Branch predictor, designed specifically to reduce the impact of conflict aliasing. Through both analytical and simulation models, we show that the skewed Branch predictor removes a substantial portion of conflict aliasing by introducing redundancy to the Branch-predictor tables. Although this redundancy increases capacity aliasing compared to a standard one-bank structure of comparable size, our simulations show that the reduction in conflict aliasing overcomes this effect to yield a gain in prediction accuracy. Alternatively, we show that a skewed organization can achieve the same prediction accuracy as a standard one-bank organization but with half the storage requirements.
Mateo Valero - One of the best experts on this subject based on the ideXlab platform.
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A Simple Speculative Load Control Mechanism for Energy Saving
2015Co-Authors: Alex Pajuelo, Oliverio J. Santana, Mateo ValeroAbstract:To alleviate the memory wall problem, current architec-tural trends suggest implementing large instruction windows able to maintain a high number of in-flight instructions. However, the benefits achieved by these recent proposals may be limited because more instructions are executed down the wrong path of a mispredicted Branch, likely polluting the processor caches. The larger number of misspeculated instructions involves increasing the energy consumed com-pared to traditional designs with smaller instruction win-dows. Our analysis shows that, for some SPEC2000 integer benchmarks, up to 2,5X wrong-path load instructions are ex-ecuted when the instruction window of a 4-way superscalar processor is increased from 256 to 1024 entries. This paper describes a simple speculative control tech-nique to prevent wrong-path load instructions from being ex-ecuted. Our technique extends the functionality of the load-store queue to block those load instructions that depend on a hard-to-predict Conditional Branch until it is resolved. If the Branch is actually mispredicted, unnecessary cache misses can be avoided, saving energy down the wrong path. Fur-thermore, instructions that depend on a blocked load are not issued because their source values are not available, which also saves energy. Our results show that the proposed mech-anism reduces, on average, up to 26 % misspeculated load instructions and 18 % wrong-path instructions without any performance loss.
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Energy saving through a simple load control mechanism
2014Co-Authors: Alex Pajuelo, Oliverio J. Santana, Mateo ValeroAbstract:To alleviate the memory wall problem, current architectural trends suggest implementing large instruction windows able to maintain a high number of in-flight instructions. How-ever, the benefits achieved by these recent proposals may be limited because more instructions are executed down the wrong path of a mispredicted Branch. The larger num-ber of misspeculated instructions involves increasing the en-ergy consumed compared to traditional designs with smaller instruction windows. Our analysis shows that, for some SPEC2000 integer benchmarks, up to 2,5X wrong-path load instructions are executed when the instruction window of a 4-way superscalar processor is increased from 256 to 1024 entries. This paper describes a simple speculative control tech-nique to prevent wrong-path load instructions from being executed. Our technique extends the functionality of the load-store queue to block those load instructions that de-pend on a hard-to-predict Conditional Branch until it is re-solved. If the Branch is actually mispredicted, unnecessary cache misses can be avoided, saving energy down the wrong path. Furthermore, instructions that depend on a blocked load are not issued because their source values are not avail-able, which also saves dynamic energy. Our results show that the proposed mechanism reduces, on average, up to 26 % misspeculated load instructions and 18 % wrong-path instructions without any performance loss
Dmitry Ponomarev - One of the best experts on this subject based on the ideXlab platform.
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Branchscope a new side channel attack on directional Branch predictor
Architectural Support for Programming Languages and Operating Systems, 2018Co-Authors: Dmitry Evtyushkin, Ryan Riley, Nael Cse, Ece Abughazaleh, Dmitry PonomarevAbstract:We present BranchScope - a new side-channel attack where the attacker infers the direction of an arbitrary Conditional Branch instruction in a victim program by manipulating the shared directional Branch predictor. The directional component of the Branch predictor stores the prediction on a given Branch (taken or not-taken) and is a different component from the Branch target buffer (BTB) attacked by previous work. BranchScope is the first fine-grained attack on the directional Branch predictor, expanding our understanding of the side channel vulnerability of the Branch prediction unit. Our attack targets complex hybrid Branch predictors with unknown organization. We demonstrate how an attacker can force these predictors to switch to a simple 1-level mode to simplify the direction recovery. We carry out BranchScope on several recent Intel CPUs and also demonstrate the attack against an SGX enclave.
Hiroshi Kadota - One of the best experts on this subject based on the ideXlab platform.
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ohmega a vlsi superscalar processor architecture for numerical applications
International Symposium on Computer Architecture, 1991Co-Authors: Masaitsu Nakajima, Hiraku Nakano, Yasuhiro Nakakura, Tadahiro Yoshida, Reiji Segawa, Takeshi Kishida, Yuji Nakai, Hiroshi KadotaAbstract:multiple instructions per clock cycle, there are at least four This paper describes a VLSI superscalar processor architecture which can sustain very high performance in numericai applications. The architecture performs instructionlevel scheduling statically by the compiler, and performs outof-order issuing and executing of instructions to decrease the stall on the pipelines that dynamically occurs in execution. In this architecture, a pair of instructions are fetched in every clock cycle, decoded simultaneously, and issued to corresponding execution pipelines independently. For ease of instruction-level scheduling by the compiler, the architecture provider: -i) rimultaneoun execution df almost all pairs of instructions including Store-Stare pair and Load-Store pair, ii) simple, low-latency, and easily-paired execution pipeline structure, and iii) high-capacity muiti-ported floating point registers and integer registers. Enhanced performance by the dynamic decrease of the pipeline hazards is achieved by i) efficient data dependency resolution with novel Directly Tag Compare (DTC) method, ii) non-penalty Branch mechanism and simple control dependency resolution, and iii) large data transfer ability by the pipelined data cache and 128 bit wide bus bandwidth. An efficient data dependency resolutioi mechanism, which is realized by using the novel DTC method, synchronized pipeiine operation, and data bypassing network, permits out-of-order instruction issuing and execution. The idea of DTC method is similar to that of dynamic data-flaw architecture with tagged token. The non-penalty Branches are realized by three techniques, delayed Branch, LOOP instruction that executer counter decrement, compare, and Branch in one clock cycle, and non-penalty Conditional Branch with predicted condition codes. These 'techniques contribute to the decrease of the pipeline stalls occurring at run time. The architecture can achieve 80MFLOPS/80MIPS peak performance at 4OMHz clock and sustain 1.4 to 3.6 times higher performance of simple Multiple Function Unit (MFU) type RISC processors by taking advantage of these techniques.