The Experts below are selected from a list of 549 Experts worldwide ranked by ideXlab platform

Sherif Welsen Shaker - One of the best experts on this subject based on the ideXlab platform.

  • Design and Implementation of Adaptive Turbo Encoder for Quantized Software Defined Low-Power DVB-RCS Radios
    Telecommunications Society Academic Mind, 2010
    Co-Authors: Salwa Elramly, Sherif Welsen Shaker
    Abstract:

    Turbo codes are employed in every robust wireless digital communications system. Those codes have been adopted for the satellite return channel in DVB-RCS (Return Channel via Satellite) standard. In Software Defined Radios (SDRs), Field Programmable Gate Array technology (FPGA) is considered a highly Configurable Option for implementing many sophisticated signal processing tasks. The implementation for such codes is complex and dissipates a large amount of power. This paper studies the efficient implementation of quantized DVB-RCS turbo coding. Also, a low-power, turbo encoder for DVB-RCS is described using a VHDL code. The proposed encoder design is implemented on Xilinx Virtex-II Pro, XC2vpx30 FPGA chip. FPGA Advantage Pro package provided by Mentor Graphics is used for VHDL description and ISE 10.1 by Xilinx is used for synthetization

  • fpga implementation of a reConfigurable viterbi decoder for wimax receiver
    International Conference on Microelectronics, 2009
    Co-Authors: Sherif Welsen Shaker, Salwa Elramly, Khaled Ali Sheriata
    Abstract:

    Field Programmable Gate Array technology (FPGA) is a highly Configurable Option for implementing many sophisticated signal processing tasks in Software Defined Radios (SDRs). Those types of radios are realized using highly Configurable hardware platforms. Convolutional codes are used in every robust digital communication system and Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. In this paper, a low power-reConfigurable Viterbi decoder for WiMAX receiver is described using a VHDL code for FPGA implementation. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vpx30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.

  • fpga implementation of a Configurable viterbi decoder for software radio receiver
    AUTOTESTCON, 2009
    Co-Authors: Sherif Welsen Shaker, Salwa Elramly, Khaled Shehata
    Abstract:

    Convolutional codes are one of the Forward Error Correction (FEC) codes that are used in every robust digital communication system. Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using highly Configurable hardware platforms. Field Programmable Gate Array technology (FPGA) is a highly Configurable Option for implementing many sophisticated signal processing tasks in SDR. In this paper, a generic, Configurable and low power Viterbi decoder for software defined radio is described using a VHDL code for FPGA implementation. The proposed design of the Viterbi decoder is considered to be generic so that it facilitates the prototyping of the decoder with different specifications. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vp30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.

  • design and implementation of low power viterbi decoder for software defined wimax receiver
    2009
    Co-Authors: Sherif Welsen Shaker, Salwa Elramly, Khaled Shehata
    Abstract:

    Viterbi algorithm is employed in wireless communications to decode the convolutional codes; those codes are used in every robust digital communication system. Such decoders are complex and dissipate large amount of power. In Software Defined Radios (SDRs), Field Programmable Gate Array technology (FPGA) is considered a highly Configurable Option for implementing many sophisticated signal processing tasks. In this paper, a low- power, adaptive Viterbi decoder for WiMAX receiver is described using a VHDL code. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vpx70 FPGA chip. FPGA Advantage Pro package provided by Mentor Graphics is used for VHDL description and ISE 10.1 by Xilinx is used for synthesization.

Khaled Shehata - One of the best experts on this subject based on the ideXlab platform.

  • fpga implementation of a Configurable viterbi decoder for software radio receiver
    AUTOTESTCON, 2009
    Co-Authors: Sherif Welsen Shaker, Salwa Elramly, Khaled Shehata
    Abstract:

    Convolutional codes are one of the Forward Error Correction (FEC) codes that are used in every robust digital communication system. Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using highly Configurable hardware platforms. Field Programmable Gate Array technology (FPGA) is a highly Configurable Option for implementing many sophisticated signal processing tasks in SDR. In this paper, a generic, Configurable and low power Viterbi decoder for software defined radio is described using a VHDL code for FPGA implementation. The proposed design of the Viterbi decoder is considered to be generic so that it facilitates the prototyping of the decoder with different specifications. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vp30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.

  • design and implementation of low power viterbi decoder for software defined wimax receiver
    2009
    Co-Authors: Sherif Welsen Shaker, Salwa Elramly, Khaled Shehata
    Abstract:

    Viterbi algorithm is employed in wireless communications to decode the convolutional codes; those codes are used in every robust digital communication system. Such decoders are complex and dissipate large amount of power. In Software Defined Radios (SDRs), Field Programmable Gate Array technology (FPGA) is considered a highly Configurable Option for implementing many sophisticated signal processing tasks. In this paper, a low- power, adaptive Viterbi decoder for WiMAX receiver is described using a VHDL code. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vpx70 FPGA chip. FPGA Advantage Pro package provided by Mentor Graphics is used for VHDL description and ISE 10.1 by Xilinx is used for synthesization.

Salwa Elramly - One of the best experts on this subject based on the ideXlab platform.

  • Design and Implementation of Adaptive Turbo Encoder for Quantized Software Defined Low-Power DVB-RCS Radios
    Telecommunications Society Academic Mind, 2010
    Co-Authors: Salwa Elramly, Sherif Welsen Shaker
    Abstract:

    Turbo codes are employed in every robust wireless digital communications system. Those codes have been adopted for the satellite return channel in DVB-RCS (Return Channel via Satellite) standard. In Software Defined Radios (SDRs), Field Programmable Gate Array technology (FPGA) is considered a highly Configurable Option for implementing many sophisticated signal processing tasks. The implementation for such codes is complex and dissipates a large amount of power. This paper studies the efficient implementation of quantized DVB-RCS turbo coding. Also, a low-power, turbo encoder for DVB-RCS is described using a VHDL code. The proposed encoder design is implemented on Xilinx Virtex-II Pro, XC2vpx30 FPGA chip. FPGA Advantage Pro package provided by Mentor Graphics is used for VHDL description and ISE 10.1 by Xilinx is used for synthetization

  • fpga implementation of a reConfigurable viterbi decoder for wimax receiver
    International Conference on Microelectronics, 2009
    Co-Authors: Sherif Welsen Shaker, Salwa Elramly, Khaled Ali Sheriata
    Abstract:

    Field Programmable Gate Array technology (FPGA) is a highly Configurable Option for implementing many sophisticated signal processing tasks in Software Defined Radios (SDRs). Those types of radios are realized using highly Configurable hardware platforms. Convolutional codes are used in every robust digital communication system and Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. In this paper, a low power-reConfigurable Viterbi decoder for WiMAX receiver is described using a VHDL code for FPGA implementation. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vpx30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.

  • fpga implementation of a Configurable viterbi decoder for software radio receiver
    AUTOTESTCON, 2009
    Co-Authors: Sherif Welsen Shaker, Salwa Elramly, Khaled Shehata
    Abstract:

    Convolutional codes are one of the Forward Error Correction (FEC) codes that are used in every robust digital communication system. Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using highly Configurable hardware platforms. Field Programmable Gate Array technology (FPGA) is a highly Configurable Option for implementing many sophisticated signal processing tasks in SDR. In this paper, a generic, Configurable and low power Viterbi decoder for software defined radio is described using a VHDL code for FPGA implementation. The proposed design of the Viterbi decoder is considered to be generic so that it facilitates the prototyping of the decoder with different specifications. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vp30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.

  • design and implementation of low power viterbi decoder for software defined wimax receiver
    2009
    Co-Authors: Sherif Welsen Shaker, Salwa Elramly, Khaled Shehata
    Abstract:

    Viterbi algorithm is employed in wireless communications to decode the convolutional codes; those codes are used in every robust digital communication system. Such decoders are complex and dissipate large amount of power. In Software Defined Radios (SDRs), Field Programmable Gate Array technology (FPGA) is considered a highly Configurable Option for implementing many sophisticated signal processing tasks. In this paper, a low- power, adaptive Viterbi decoder for WiMAX receiver is described using a VHDL code. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vpx70 FPGA chip. FPGA Advantage Pro package provided by Mentor Graphics is used for VHDL description and ISE 10.1 by Xilinx is used for synthesization.

Khaled Ali Sheriata - One of the best experts on this subject based on the ideXlab platform.

  • fpga implementation of a reConfigurable viterbi decoder for wimax receiver
    International Conference on Microelectronics, 2009
    Co-Authors: Sherif Welsen Shaker, Salwa Elramly, Khaled Ali Sheriata
    Abstract:

    Field Programmable Gate Array technology (FPGA) is a highly Configurable Option for implementing many sophisticated signal processing tasks in Software Defined Radios (SDRs). Those types of radios are realized using highly Configurable hardware platforms. Convolutional codes are used in every robust digital communication system and Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. In this paper, a low power-reConfigurable Viterbi decoder for WiMAX receiver is described using a VHDL code for FPGA implementation. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vpx30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.

Evan Greenland - One of the best experts on this subject based on the ideXlab platform.

  • Active File System
    2000
    Co-Authors: Deb Deppeler, Evan Greenland
    Abstract:

    The Active File System (active), an extension of the minix file system for Linux, provides automatic logging of individual file operations. In addition, we present a prototype of a file access auditing system as a Configurable Option available both internally within the active module and as an external user level program which communicates with the file system module and describe how the prototype can be extended to support the execution of arbitrary user commands in response to file operations. Timing tests are provided that prove the viability of these different approaches.