The Experts below are selected from a list of 231 Experts worldwide ranked by ideXlab platform

Weifeng He - One of the best experts on this subject based on the ideXlab platform.

  • ICCAD - Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs
    2015 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2015
    Co-Authors: Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He
    Abstract:

    Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (Field Programmable Gate Arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the Configuration Bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in real FPGAs, DWR leverages redundant resources for interconnect duplication and enables fault recovery with lightweight circuit-level support. Compared with traditional fault tolerant techniques, DWR retains the fault recovering capability but eliminates expensive copies. The experimental results show that a large portion of the interconnects can be protected, which in consequence significantly reduces the vulnerable Configuration Bits. In addition, DWR does not alter the placement and routing from standard design flow, and therefore does not affect the design closure but greatly improves the design reliability in a cost-effective way.

  • Redundancy based interconnect duplication to mitigate soft errors in SRAM-based FPGAs
    2015 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2015
    Co-Authors: Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He
    Abstract:

    Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (Field Programmable Gate Arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the Configuration Bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in real FPGAs, DWR leverages redundant resources for interconnect duplication and enables fault recovery with lightweight circuit-level support. Compared with traditional fault tolerant techniques, DWR retains the fault recovering capability but eliminates expensive copies. The experimental results show that a large portion of the interconnects can be protected, which in consequence significantly reduces the vulnerable Configuration Bits. In addition, DWR does not alter the placement and routing from standard design flow, and therefore does not affect the design closure but greatly improves the design reliability in a cost-effective way.

  • SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
    ACM Transactions on Design Automation of Electronic Systems, 2013
    Co-Authors: Naifeng Jing, Weifeng He, Zhe Feng, Lei He
    Abstract:

    Reliability has become an increasingly important concern for SRAM-based field programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based FPGAs, this article first develops an SEU evaluation framework that can quantify the failure sensitivity for each Configuration Bit during design time. This framework considers detailed fault behavior and logic masking on a post-layout FPGA application and performs logic simulation on various circuit elements for fault evaluation. Applying this framework on MCNC benchmark circuits, we first characterize SEUs with respect to different FPGA circuits and architectures, for example, bidirectional routing and unidirectional routing. We show that in both routing architectures, interconnects not only contribute to the lion's share of the SEU-induced functional failures, but also present higher failure rates per Configuration Bits than LUTs. Particularly, local interconnect multiplexers in logic blocks have the highest failure rate per Configuration Bit. Then, we evaluate three recently proposed SEU mitigation algorithms, IPD, IPF, and IPV, which are all logic resynthesis-based with little or no overhead on placement and routing. Different fault mitigating capabilities at the chip level are revealed, and it demonstrates that algorithms with explicit consideration for interconnect significantly mitigate the SEU at the chip level, for example, IPV achieves 61p failure rate reduction on average against IPF with about 15p. In addition, the combination of the three algorithms delivers over 70p failure rate reduction on average at the chip level. The experiments also reveal that in order to improve fault tolerance at the chip level, it is necessary for future fault mitigation algorithms to concern not only LUT or interconnect faults, but also their interactions. We envision that our framework can be used to cast more useful insights for more robust FPGA circuits, architectures, and better synthesis algorithms.

  • FPL - Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms
    2011 21st International Conference on Field Programmable Logic and Applications, 2011
    Co-Authors: Naifeng Jing, Weifeng He, Zhe Feng, Rick Wong, Lei He
    Abstract:

    This paper studies the SEU (Single Event Upset) fault for SRAM-based FPGAs. Considering detailed fault behavior on various circuit elements in a post-layout FPGA application, we develop a simulation-based SEU evaluation tool that quantifies fault contribution for each Configuration Bit. Using this tool and MCNC benchmark circuits, we study the fault characteristics of FPGA circuits and architectures. We show that interconnects not only contribute to the lion share of functional failures, but also have higher failure rate per Configuration Bit than LUTs. Particularly, multiplexers in local interconnects have the highest failure rate per Bit. We find that tuning LUT and cluster sizes helps to reduce the rate (up to 38% in our experiments). In addition, we evaluate two recent fault mitigation algorithms IPD and IPF, which reduce LUT faults by an average of 74% and 15% respectively. But when interconnects are taken into account, the reduction via IPD which considers only LUT faults is merely 6% on chip level. Yet the reduction via IPF which implicitly considers interconnect faults is still around 15%. Therefore, synthesis algorithm should be evaluated with interconnect faults and future algorithms should be developed with consideration of interconnect faults explicitly.

Naifeng Jing - One of the best experts on this subject based on the ideXlab platform.

  • ICCAD - Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs
    2015 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2015
    Co-Authors: Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He
    Abstract:

    Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (Field Programmable Gate Arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the Configuration Bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in real FPGAs, DWR leverages redundant resources for interconnect duplication and enables fault recovery with lightweight circuit-level support. Compared with traditional fault tolerant techniques, DWR retains the fault recovering capability but eliminates expensive copies. The experimental results show that a large portion of the interconnects can be protected, which in consequence significantly reduces the vulnerable Configuration Bits. In addition, DWR does not alter the placement and routing from standard design flow, and therefore does not affect the design closure but greatly improves the design reliability in a cost-effective way.

  • Redundancy based interconnect duplication to mitigate soft errors in SRAM-based FPGAs
    2015 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2015
    Co-Authors: Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He
    Abstract:

    Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (Field Programmable Gate Arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the Configuration Bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in real FPGAs, DWR leverages redundant resources for interconnect duplication and enables fault recovery with lightweight circuit-level support. Compared with traditional fault tolerant techniques, DWR retains the fault recovering capability but eliminates expensive copies. The experimental results show that a large portion of the interconnects can be protected, which in consequence significantly reduces the vulnerable Configuration Bits. In addition, DWR does not alter the placement and routing from standard design flow, and therefore does not affect the design closure but greatly improves the design reliability in a cost-effective way.

  • SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
    ACM Transactions on Design Automation of Electronic Systems, 2013
    Co-Authors: Naifeng Jing, Weifeng He, Zhe Feng, Lei He
    Abstract:

    Reliability has become an increasingly important concern for SRAM-based field programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based FPGAs, this article first develops an SEU evaluation framework that can quantify the failure sensitivity for each Configuration Bit during design time. This framework considers detailed fault behavior and logic masking on a post-layout FPGA application and performs logic simulation on various circuit elements for fault evaluation. Applying this framework on MCNC benchmark circuits, we first characterize SEUs with respect to different FPGA circuits and architectures, for example, bidirectional routing and unidirectional routing. We show that in both routing architectures, interconnects not only contribute to the lion's share of the SEU-induced functional failures, but also present higher failure rates per Configuration Bits than LUTs. Particularly, local interconnect multiplexers in logic blocks have the highest failure rate per Configuration Bit. Then, we evaluate three recently proposed SEU mitigation algorithms, IPD, IPF, and IPV, which are all logic resynthesis-based with little or no overhead on placement and routing. Different fault mitigating capabilities at the chip level are revealed, and it demonstrates that algorithms with explicit consideration for interconnect significantly mitigate the SEU at the chip level, for example, IPV achieves 61p failure rate reduction on average against IPF with about 15p. In addition, the combination of the three algorithms delivers over 70p failure rate reduction on average at the chip level. The experiments also reveal that in order to improve fault tolerance at the chip level, it is necessary for future fault mitigation algorithms to concern not only LUT or interconnect faults, but also their interactions. We envision that our framework can be used to cast more useful insights for more robust FPGA circuits, architectures, and better synthesis algorithms.

  • FPL - Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms
    2011 21st International Conference on Field Programmable Logic and Applications, 2011
    Co-Authors: Naifeng Jing, Weifeng He, Zhe Feng, Rick Wong, Lei He
    Abstract:

    This paper studies the SEU (Single Event Upset) fault for SRAM-based FPGAs. Considering detailed fault behavior on various circuit elements in a post-layout FPGA application, we develop a simulation-based SEU evaluation tool that quantifies fault contribution for each Configuration Bit. Using this tool and MCNC benchmark circuits, we study the fault characteristics of FPGA circuits and architectures. We show that interconnects not only contribute to the lion share of functional failures, but also have higher failure rate per Configuration Bit than LUTs. Particularly, multiplexers in local interconnects have the highest failure rate per Bit. We find that tuning LUT and cluster sizes helps to reduce the rate (up to 38% in our experiments). In addition, we evaluate two recent fault mitigation algorithms IPD and IPF, which reduce LUT faults by an average of 74% and 15% respectively. But when interconnects are taken into account, the reduction via IPD which considers only LUT faults is merely 6% on chip level. Yet the reduction via IPF which implicitly considers interconnect faults is still around 15%. Therefore, synthesis algorithm should be evaluated with interconnect faults and future algorithms should be developed with consideration of interconnect faults explicitly.

Xin Chen - One of the best experts on this subject based on the ideXlab platform.

  • ICCAD - Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs
    2015 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2015
    Co-Authors: Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He
    Abstract:

    Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (Field Programmable Gate Arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the Configuration Bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in real FPGAs, DWR leverages redundant resources for interconnect duplication and enables fault recovery with lightweight circuit-level support. Compared with traditional fault tolerant techniques, DWR retains the fault recovering capability but eliminates expensive copies. The experimental results show that a large portion of the interconnects can be protected, which in consequence significantly reduces the vulnerable Configuration Bits. In addition, DWR does not alter the placement and routing from standard design flow, and therefore does not affect the design closure but greatly improves the design reliability in a cost-effective way.

  • Redundancy based interconnect duplication to mitigate soft errors in SRAM-based FPGAs
    2015 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2015
    Co-Authors: Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He
    Abstract:

    Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (Field Programmable Gate Arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the Configuration Bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in real FPGAs, DWR leverages redundant resources for interconnect duplication and enables fault recovery with lightweight circuit-level support. Compared with traditional fault tolerant techniques, DWR retains the fault recovering capability but eliminates expensive copies. The experimental results show that a large portion of the interconnects can be protected, which in consequence significantly reduces the vulnerable Configuration Bits. In addition, DWR does not alter the placement and routing from standard design flow, and therefore does not affect the design closure but greatly improves the design reliability in a cost-effective way.

Jiacheng Zhou - One of the best experts on this subject based on the ideXlab platform.

  • ICCAD - Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs
    2015 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2015
    Co-Authors: Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He
    Abstract:

    Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (Field Programmable Gate Arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the Configuration Bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in real FPGAs, DWR leverages redundant resources for interconnect duplication and enables fault recovery with lightweight circuit-level support. Compared with traditional fault tolerant techniques, DWR retains the fault recovering capability but eliminates expensive copies. The experimental results show that a large portion of the interconnects can be protected, which in consequence significantly reduces the vulnerable Configuration Bits. In addition, DWR does not alter the placement and routing from standard design flow, and therefore does not affect the design closure but greatly improves the design reliability in a cost-effective way.

  • Redundancy based interconnect duplication to mitigate soft errors in SRAM-based FPGAs
    2015 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2015
    Co-Authors: Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He
    Abstract:

    Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (Field Programmable Gate Arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the Configuration Bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in real FPGAs, DWR leverages redundant resources for interconnect duplication and enables fault recovery with lightweight circuit-level support. Compared with traditional fault tolerant techniques, DWR retains the fault recovering capability but eliminates expensive copies. The experimental results show that a large portion of the interconnects can be protected, which in consequence significantly reduces the vulnerable Configuration Bits. In addition, DWR does not alter the placement and routing from standard design flow, and therefore does not affect the design closure but greatly improves the design reliability in a cost-effective way.

Jianfei Jiang - One of the best experts on this subject based on the ideXlab platform.

  • ICCAD - Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs
    2015 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2015
    Co-Authors: Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He
    Abstract:

    Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (Field Programmable Gate Arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the Configuration Bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in real FPGAs, DWR leverages redundant resources for interconnect duplication and enables fault recovery with lightweight circuit-level support. Compared with traditional fault tolerant techniques, DWR retains the fault recovering capability but eliminates expensive copies. The experimental results show that a large portion of the interconnects can be protected, which in consequence significantly reduces the vulnerable Configuration Bits. In addition, DWR does not alter the placement and routing from standard design flow, and therefore does not affect the design closure but greatly improves the design reliability in a cost-effective way.

  • Redundancy based interconnect duplication to mitigate soft errors in SRAM-based FPGAs
    2015 IEEE ACM International Conference on Computer-Aided Design (ICCAD), 2015
    Co-Authors: Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He
    Abstract:

    Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (Field Programmable Gate Arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the Configuration Bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in real FPGAs, DWR leverages redundant resources for interconnect duplication and enables fault recovery with lightweight circuit-level support. Compared with traditional fault tolerant techniques, DWR retains the fault recovering capability but eliminates expensive copies. The experimental results show that a large portion of the interconnects can be protected, which in consequence significantly reduces the vulnerable Configuration Bits. In addition, DWR does not alter the placement and routing from standard design flow, and therefore does not affect the design closure but greatly improves the design reliability in a cost-effective way.