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J. Becker - One of the best experts on this subject based on the ideXlab platform.
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Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures supPort dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an internal Configuration Port. The Virtex II / IV and V architectures all include the ICAP Port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual internal Configuration Port for the Spartan III family of FPGAs. The Configuration Port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
K. Paulsson - One of the best experts on this subject based on the ideXlab platform.
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Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures supPort dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an internal Configuration Port. The Virtex II / IV and V architectures all include the ICAP Port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual internal Configuration Port for the Spartan III family of FPGAs. The Configuration Port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
M. Hubner - One of the best experts on this subject based on the ideXlab platform.
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Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures supPort dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an internal Configuration Port. The Virtex II / IV and V architectures all include the ICAP Port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual internal Configuration Port for the Spartan III family of FPGAs. The Configuration Port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
G. Auer - One of the best experts on this subject based on the ideXlab platform.
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Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures supPort dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an internal Configuration Port. The Virtex II / IV and V architectures all include the ICAP Port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual internal Configuration Port for the Spartan III family of FPGAs. The Configuration Port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.
M. Dreschmann - One of the best experts on this subject based on the ideXlab platform.
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Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-ReConfiguration on Xilinx Spartan III FPGAs
2007 International Conference on Field Programmable Logic and Applications, 2007Co-Authors: K. Paulsson, M. Hubner, G. Auer, M. Dreschmann, L. Chen, J. BeckerAbstract:The exploitation of dynamic and partial hardware reConfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures supPort dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an internal Configuration Port. The Virtex II / IV and V architectures all include the ICAP Port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual internal Configuration Port for the Spartan III family of FPGAs. The Configuration Port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.