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Chandan Kumar Sarkar - One of the best experts on this subject based on the ideXlab platform.
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Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit
arXiv: Other Computer Science, 2013Co-Authors: Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar SarkarAbstract:A modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with a few modifications. Furthermore, a detailed comparison of its performance with some of the other conventional Power Gating schemes; such as Cluster Based Sleep Transistor Design (CBSTD), Distributed Sleep Transistor Network (DSTN) etc.; has also been presented here. Considering the constraints of power consumption, performance, and the area overhead, while doing the actual implementation of any Power Gating scheme, it becomes important to deal with the various design issues like the proper sizing of the sleep transistors (STs), controlling the voltage drop (IR drop) across the STs, and obviously maintaining a desired performance with lower amount of delay degradation. With this notion, we tried to find out an efficient Power Gating strategy which can reduce the overall power consumption of any CMOS circuit by virtue of reducing the standby mode leakage current. Taking the different performance parameters into account, for an example circuit, which is actually the conventional 4x4 multiplier design, we found that the modified tunable sleep transistor cell Power Gating gives very much promising results. The reported architecture of the 4x4 multiplier with the tunable sleep transistor cell Power Gating, is designed using 45 nm technology and it consumes 1.3638x10-5 Watt of Average Power while being operated with the nominal case of the bit Configuration Word, that is, 1000.
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Implementation of the Cluster based Tunable Sleep Transistor Cell Power Gating Technique for a 4×4 Multiplier Circuit
International Journal of Computer Applications, 2013Co-Authors: Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar SarkarAbstract:modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with a few modifications. Furthermore, a detailed comparison of its performance with some of the other conventional Power Gating schemes; such as Cluster Based Sleep Transistor Design (CBSTD), Distributed Sleep Transistor Network (DSTN) etc.; has also been presented here. Considering the constraints of power consumption, performance, and the area overhead, while doing the actual implementation of any Power Gating scheme, it becomes important to deal with the various design issues like the proper sizing of the sleep transistors (STs), controlling the voltage drop (IR drop) across the STs, and obviously maintaining a desired performance with lower amount of delay degradation. With this notion, we tried to find out an efficient Power Gating strategy which can reduce the overall power consumption of any CMOS circuit by virtue of reducing the standby mode leakage current. Taking the different performance parameters into account, for an example circuit, which is actually the conventional 4×4 multiplier design, we found that the modified tunable sleep transistor cell Power Gating gives very much promising results. The reported architecture of the 4×4 multiplier with the tunable sleep transistor cell Power Gating, is designed using 45 nm technology and it consumes 1.3638×10 -5 Watt of Average Power while being operated with the nominal case of the bit Configuration Word, that is, "1000". At the same time, this design provides a delay of 2.5455×10 -10 second, which conveys a 2.29% improvement in theperformance with respect to the best case delay as obtained in case of the conventional Power Gating scheme. The entire simulation work has been done using SPICE, whereas the results are obtained for a Supply Voltage (Vdd) of 1 Volt and a frequency of 200 MHz.
Wang Hua - One of the best experts on this subject based on the ideXlab platform.
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FPGA-Based Efficient Programmable Polyphase FIR Filter
2005Co-Authors: Wang HuaAbstract:The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable Configuration Word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient Word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of (160 MHz.)
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Design and implementation of a high-speed programmable polyphase FIR filter
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03, 2003Co-Authors: Xiong Chenghuan, Zhong Shun'an, Wang HuaAbstract:FIR filters that provide linear phases are frequently used in digital signal processing, voice and data transmission. Polyphase FIR filters are applied in many practical applications of DSPs that require the sampling rate of a signal to be changed. This paper describes the design and implementation of a high-speed programmable polyphase FIR filter. The FIR is designed to run automatically under all conditions according to the programmable Configuration Word including symmetry/asymmetry, odd/even taps, and 32 taps up to 256 taps. The maximum sampling frequency is obtained as 100MHz.
Dipankar Saha - One of the best experts on this subject based on the ideXlab platform.
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Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit
arXiv: Other Computer Science, 2013Co-Authors: Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar SarkarAbstract:A modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with a few modifications. Furthermore, a detailed comparison of its performance with some of the other conventional Power Gating schemes; such as Cluster Based Sleep Transistor Design (CBSTD), Distributed Sleep Transistor Network (DSTN) etc.; has also been presented here. Considering the constraints of power consumption, performance, and the area overhead, while doing the actual implementation of any Power Gating scheme, it becomes important to deal with the various design issues like the proper sizing of the sleep transistors (STs), controlling the voltage drop (IR drop) across the STs, and obviously maintaining a desired performance with lower amount of delay degradation. With this notion, we tried to find out an efficient Power Gating strategy which can reduce the overall power consumption of any CMOS circuit by virtue of reducing the standby mode leakage current. Taking the different performance parameters into account, for an example circuit, which is actually the conventional 4x4 multiplier design, we found that the modified tunable sleep transistor cell Power Gating gives very much promising results. The reported architecture of the 4x4 multiplier with the tunable sleep transistor cell Power Gating, is designed using 45 nm technology and it consumes 1.3638x10-5 Watt of Average Power while being operated with the nominal case of the bit Configuration Word, that is, 1000.
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Implementation of the Cluster based Tunable Sleep Transistor Cell Power Gating Technique for a 4×4 Multiplier Circuit
International Journal of Computer Applications, 2013Co-Authors: Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar SarkarAbstract:modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with a few modifications. Furthermore, a detailed comparison of its performance with some of the other conventional Power Gating schemes; such as Cluster Based Sleep Transistor Design (CBSTD), Distributed Sleep Transistor Network (DSTN) etc.; has also been presented here. Considering the constraints of power consumption, performance, and the area overhead, while doing the actual implementation of any Power Gating scheme, it becomes important to deal with the various design issues like the proper sizing of the sleep transistors (STs), controlling the voltage drop (IR drop) across the STs, and obviously maintaining a desired performance with lower amount of delay degradation. With this notion, we tried to find out an efficient Power Gating strategy which can reduce the overall power consumption of any CMOS circuit by virtue of reducing the standby mode leakage current. Taking the different performance parameters into account, for an example circuit, which is actually the conventional 4×4 multiplier design, we found that the modified tunable sleep transistor cell Power Gating gives very much promising results. The reported architecture of the 4×4 multiplier with the tunable sleep transistor cell Power Gating, is designed using 45 nm technology and it consumes 1.3638×10 -5 Watt of Average Power while being operated with the nominal case of the bit Configuration Word, that is, "1000". At the same time, this design provides a delay of 2.5455×10 -10 second, which conveys a 2.29% improvement in theperformance with respect to the best case delay as obtained in case of the conventional Power Gating scheme. The entire simulation work has been done using SPICE, whereas the results are obtained for a Supply Voltage (Vdd) of 1 Volt and a frequency of 200 MHz.
Hiromu Sakai - One of the best experts on this subject based on the ideXlab platform.
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The Interplay of Relational and Non-relational Processes in Sentence Production: The Case of Relative Clause Planning in Japanese and Spanish.
Frontiers in psychology, 2018Co-Authors: Laura Rodrigo, José Manuel Igoa, Hiromu SakaiAbstract:Speech planning involves different steps in order to transform a conceptual message into speech. These include establishing structural relations among constituents (i.e., relational information), and selecting the appropriate lexical items to convey the intended message (non-relational elements). However, the precise way relational and non-relational information are computed when undertaking linguistic encoding is not clear. This paper explores how the pre-linguistic message undergoes linguistic encoding, and what kind of information (relational or non-relational) is prioritized in doing so. We analyze the production planning of Relative Clauses in Spanish (a head-initial language) and Japanese (a head-final language) by monolingual speakers, by means of the eye-tracking method while participants described colored pictures. Although in both Spanish and Japanese the structure under study is the same (with the same syntactic Configuration), Word order is entirely opposite between both languages. In Japanese, the head noun is not uttered until the end of the clause, thus making it possible to explore sentence planning in a structure where the syntactically most dominant element (the head noun, HN) is not the first element. Variables tested were type of relative clause, with either the agent or the patient as head noun, and the animacy of the agent and the patient of the event, the latter allowing the manipulation of the conceptual saliency of the elements involved. Results showed Japanese speakers focus extensively on the HN before directing their gazes to the element they are going to utter first, suggesting a speech planning process that prioritizes relational information, that is, structural scaffolding. Spanish monolinguals, in turn, showed a pattern in which both structural and linear information appear to be more closely related from the beginning. In both languages, the animacy of isolated elements had little effect on gaze patterns. Results point to a planning process that prioritizes structural relations over access to lexical elements in order in the planning of complex structures, with room for flexibility when the grammar of the language allows so.
Sayan Chatterjee - One of the best experts on this subject based on the ideXlab platform.
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Implementation of the Cluster Based Tunable Sleep Transistor Cell Power Gating Technique for a 4x4 Multiplier Circuit
arXiv: Other Computer Science, 2013Co-Authors: Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar SarkarAbstract:A modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with a few modifications. Furthermore, a detailed comparison of its performance with some of the other conventional Power Gating schemes; such as Cluster Based Sleep Transistor Design (CBSTD), Distributed Sleep Transistor Network (DSTN) etc.; has also been presented here. Considering the constraints of power consumption, performance, and the area overhead, while doing the actual implementation of any Power Gating scheme, it becomes important to deal with the various design issues like the proper sizing of the sleep transistors (STs), controlling the voltage drop (IR drop) across the STs, and obviously maintaining a desired performance with lower amount of delay degradation. With this notion, we tried to find out an efficient Power Gating strategy which can reduce the overall power consumption of any CMOS circuit by virtue of reducing the standby mode leakage current. Taking the different performance parameters into account, for an example circuit, which is actually the conventional 4x4 multiplier design, we found that the modified tunable sleep transistor cell Power Gating gives very much promising results. The reported architecture of the 4x4 multiplier with the tunable sleep transistor cell Power Gating, is designed using 45 nm technology and it consumes 1.3638x10-5 Watt of Average Power while being operated with the nominal case of the bit Configuration Word, that is, 1000.
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Implementation of the Cluster based Tunable Sleep Transistor Cell Power Gating Technique for a 4×4 Multiplier Circuit
International Journal of Computer Applications, 2013Co-Authors: Dipankar Saha, Subhramita Basak, Sagar Mukherjee, Sayan Chatterjee, Chandan Kumar SarkarAbstract:modular, programmable, and high performance Power Gating strategy, called cluster based tunable sleep transistor cell Power Gating, has been introduced in the present paper with a few modifications. Furthermore, a detailed comparison of its performance with some of the other conventional Power Gating schemes; such as Cluster Based Sleep Transistor Design (CBSTD), Distributed Sleep Transistor Network (DSTN) etc.; has also been presented here. Considering the constraints of power consumption, performance, and the area overhead, while doing the actual implementation of any Power Gating scheme, it becomes important to deal with the various design issues like the proper sizing of the sleep transistors (STs), controlling the voltage drop (IR drop) across the STs, and obviously maintaining a desired performance with lower amount of delay degradation. With this notion, we tried to find out an efficient Power Gating strategy which can reduce the overall power consumption of any CMOS circuit by virtue of reducing the standby mode leakage current. Taking the different performance parameters into account, for an example circuit, which is actually the conventional 4×4 multiplier design, we found that the modified tunable sleep transistor cell Power Gating gives very much promising results. The reported architecture of the 4×4 multiplier with the tunable sleep transistor cell Power Gating, is designed using 45 nm technology and it consumes 1.3638×10 -5 Watt of Average Power while being operated with the nominal case of the bit Configuration Word, that is, "1000". At the same time, this design provides a delay of 2.5455×10 -10 second, which conveys a 2.29% improvement in theperformance with respect to the best case delay as obtained in case of the conventional Power Gating scheme. The entire simulation work has been done using SPICE, whereas the results are obtained for a Supply Voltage (Vdd) of 1 Volt and a frequency of 200 MHz.