The Experts below are selected from a list of 23739 Experts worldwide ranked by ideXlab platform

Nisheeth K Vishnoi - One of the best experts on this subject based on the ideXlab platform.

  • unique games on expanding Constraint Graphs are easy
    Symposium on the Theory of Computing, 2008
    Co-Authors: Sanjeev Arora, Alexandra Kolla, David Steurer, Madhur Tulsiani, Subhash A Knot, Nisheeth K Vishnoi
    Abstract:

    We present an efficient algorithm to find a good solution to the Unique Games problem when the Constraint Graph is an expander. We introduce a new analysis of the standard SDP in this case that involves correlations among distant vertices. It also leads to a parallel repetition theorem for unique games when the Graph is an expander.

  • unique games on expanding Constraint Graphs are easy extended abstract
    Symposium on the Theory of Computing, 2008
    Co-Authors: Sanjeev Arora, Subhash Khot, Alexandra Kolla, David Steurer, Madhur Tulsiani, Nisheeth K Vishnoi
    Abstract:

    We present an efficient algorithm to find a good solution to the Unique Games problem when the Constraint Graph is an expander. We introduce a new analysis of the standard SDP in this case that involves correlations among distant vertices. It also leads to a parallel repetition theorem for unique games when the Graph is an expander.

  • STOC - Unique games on expanding Constraint Graphs are easy: extended abstract
    Proceedings of the fourtieth annual ACM symposium on Theory of computing - STOC 08, 2008
    Co-Authors: Sanjeev Arora, Subhash Khot, Alexandra Kolla, David Steurer, Madhur Tulsiani, Nisheeth K Vishnoi
    Abstract:

    We present an efficient algorithm to find a good solution to the Unique Games problem when the Constraint Graph is an expander. We introduce a new analysis of the standard SDP in this case that involves correlations among distant vertices. It also leads to a parallel repetition theorem for unique games when the Graph is an expander.

Yungchung Chang - One of the best experts on this subject based on the ideXlab platform.

  • Constraint Graph based macro placement for modern mixed size circuit designs
    International Conference on Computer Aided Design, 2008
    Co-Authors: Hsinchen Chen, Yilin Chuang, Yaowen Chang, Yungchung Chang
    Abstract:

    In this paper, we propose a Constraint Graph-based macro placement algorithm that removes macro overlaps and optimizes macro positions for modern mixed-size circuit designs. Improving over the Constraint Graph by working only on its essential edges without loss of the solution quality, our algorithm can search for high-quality macro placement solutions effectively and efficiently. Instead of packing macros along chip boundaries like most recent previous work, our placer can determine a non-compacted macro placement by linear programming and placement region cost evaluation and handle various placement Constraints/objectives. Compared with various leading academic macro placers, our algorithm can consistently and significantly reduce the wirelengths for designs with different utilization rates, implying that our macro placer is robust and has very high quality.

  • ICCAD - Constraint Graph-based macro placement for modern mixed-size circuit designs
    2008 IEEE ACM International Conference on Computer-Aided Design, 2008
    Co-Authors: Hsinchen Chen, Yilin Chuang, Yaowen Chang, Yungchung Chang
    Abstract:

    In this paper, we propose a Constraint Graph-based macro placement algorithm that removes macro overlaps and optimizes macro positions for modern mixed-size circuit designs. Improving over the Constraint Graph by working only on its essential edges without loss of the solution quality, our algorithm can search for high-quality macro placement solutions effectively and efficiently. Instead of packing macros along chip boundaries like most recent previous work, our placer can determine a non-compacted macro placement by linear programming and placement region cost evaluation and handle various placement Constraints/objectives. Compared with various leading academic macro placers, our algorithm can consistently and significantly reduce the wirelengths for designs with different utilization rates, implying that our macro placer is robust and has very high quality.

Sanjeev Arora - One of the best experts on this subject based on the ideXlab platform.

  • unique games on expanding Constraint Graphs are easy
    Symposium on the Theory of Computing, 2008
    Co-Authors: Sanjeev Arora, Alexandra Kolla, David Steurer, Madhur Tulsiani, Subhash A Knot, Nisheeth K Vishnoi
    Abstract:

    We present an efficient algorithm to find a good solution to the Unique Games problem when the Constraint Graph is an expander. We introduce a new analysis of the standard SDP in this case that involves correlations among distant vertices. It also leads to a parallel repetition theorem for unique games when the Graph is an expander.

  • unique games on expanding Constraint Graphs are easy extended abstract
    Symposium on the Theory of Computing, 2008
    Co-Authors: Sanjeev Arora, Subhash Khot, Alexandra Kolla, David Steurer, Madhur Tulsiani, Nisheeth K Vishnoi
    Abstract:

    We present an efficient algorithm to find a good solution to the Unique Games problem when the Constraint Graph is an expander. We introduce a new analysis of the standard SDP in this case that involves correlations among distant vertices. It also leads to a parallel repetition theorem for unique games when the Graph is an expander.

  • STOC - Unique games on expanding Constraint Graphs are easy: extended abstract
    Proceedings of the fourtieth annual ACM symposium on Theory of computing - STOC 08, 2008
    Co-Authors: Sanjeev Arora, Subhash Khot, Alexandra Kolla, David Steurer, Madhur Tulsiani, Nisheeth K Vishnoi
    Abstract:

    We present an efficient algorithm to find a good solution to the Unique Games problem when the Constraint Graph is an expander. We introduce a new analysis of the standard SDP in this case that involves correlations among distant vertices. It also leads to a parallel repetition theorem for unique games when the Graph is an expander.

Osamu Tatebe - One of the best experts on this subject based on the ideXlab platform.

  • workflow scheduling to minimize data movement using multi Constraint Graph partitioning
    Cluster Computing and the Grid, 2012
    Co-Authors: Masahiro Tanaka, Osamu Tatebe
    Abstract:

    Among scheduling algorithms of scientific workflows, the Graph partitioning is a technique to minimize data transfer between nodes or clusters. However, when the Graph partitioning is simply applied to a complex workflow DAG, tasks in each parallel phase are not always evenly assigned to computation nodes since the Graph partitioning algorithm is not aware of edge directions that represent task dependencies. Thus, we propose a new method of task assignment based on Multi-Constraint Graph Partitioning. This method relates the dimension of weight vectors to the rank of a task phase defined by traversing the task Graph. Our algorithm is implemented in the Pwrake workflow system and evaluated the performance of the Montage workflow using a computer cluster. The result shows that the file size accessed from remote nodes is reduced from 88% to 14% of the total file size accessed during the workflow and that the elapsed time is reduced by 31%.

  • CCGRID - Workflow Scheduling to Minimize Data Movement Using Multi-Constraint Graph Partitioning
    2012 12th IEEE ACM International Symposium on Cluster Cloud and Grid Computing (ccgrid 2012), 2012
    Co-Authors: Masahiro Tanaka, Osamu Tatebe
    Abstract:

    Among scheduling algorithms of scientific workflows, the Graph partitioning is a technique to minimize data transfer between nodes or clusters. However, when the Graph partitioning is simply applied to a complex workflow DAG, tasks in each parallel phase are not always evenly assigned to computation nodes since the Graph partitioning algorithm is not aware of edge directions that represent task dependencies. Thus, we propose a new method of task assignment based on Multi-Constraint Graph Partitioning. This method relates the dimension of weight vectors to the rank of a task phase defined by traversing the task Graph. Our algorithm is implemented in the Pwrake workflow system and evaluated the performance of the Montage workflow using a computer cluster. The result shows that the file size accessed from remote nodes is reduced from 88% to 14% of the total file size accessed during the workflow and that the elapsed time is reduced by 31%.

Mineo Kaneko - One of the best experts on this subject based on the ideXlab platform.

  • timing test scheduling for Constraint Graph based post silicon skew tuning
    International Conference on Computer Design, 2012
    Co-Authors: Mineo Kaneko
    Abstract:

    Post-Silicon Tuning is an emerging technology for improving performance-yield of VLSIs under process variations. This paper focuses especially on the post-silicon timing-skew tuning (PSST) via programmable delay elements (PDEs), and proposes a novel tuning algorithm which utilizes only the result of setup and hold timing tests, not the result of costly delay-time measurements. The basic framework of our PSST consists of the construction of Control-value Constraint Graph from the results of timing-tests, and the computation of longest path lengths on this Graph for finding safe PDE setting. Even though the cost for timing test is smaller than a delay-time measurement, the cost of timing-tests is still a dominant part of the PSST cost, and its reduction is a crucial problem. Longest path lengths which we need to compute depends directly on edge weights in the “longest-paths tree”, but for co-tree edges, their exact edge weights are not always necessary. Based on this observation, we propose timing-test scheduling for reducing the timing-test cost for PDE tuning. The experimental simulation results show that our approach reduces the test cost by almost half or more.

  • ICCD - Timing-test scheduling for Constraint-Graph based post-silicon skew tuning
    2012 IEEE 30th International Conference on Computer Design (ICCD), 2012
    Co-Authors: Mineo Kaneko
    Abstract:

    Post-Silicon Tuning is an emerging technology for improving performance-yield of VLSIs under process variations. This paper focuses especially on the post-silicon timing-skew tuning (PSST) via programmable delay elements (PDEs), and proposes a novel tuning algorithm which utilizes only the result of setup and hold timing tests, not the result of costly delay-time measurements. The basic framework of our PSST consists of the construction of Control-value Constraint Graph from the results of timing-tests, and the computation of longest path lengths on this Graph for finding safe PDE setting. Even though the cost for timing test is smaller than a delay-time measurement, the cost of timing-tests is still a dominant part of the PSST cost, and its reduction is a crucial problem. Longest path lengths which we need to compute depends directly on edge weights in the “longest-paths tree”, but for co-tree edges, their exact edge weights are not always necessary. Based on this observation, we propose timing-test scheduling for reducing the timing-test cost for PDE tuning. The experimental simulation results show that our approach reduces the test cost by almost half or more.