The Experts below are selected from a list of 103902 Experts worldwide ranked by ideXlab platform
E Nagahama - One of the best experts on this subject based on the ideXlab platform.
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heterogeneous multi Core Architecture that enables 54x aac lc stereo encoding
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, T Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, E NagahamaAbstract:This paper describes a heterogeneous multi-Core processor (HMCP) Architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory Architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-Core having homogeneous processor Cores and dynamically reconfigurable processor (DRP) ACC Cores in a preliminary evaluation of the HMCP Architecture. The performance evaluation revealed that 54times AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1- 2 min.
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heterogeneous multi Core Architecture that enables 54x aac lc stereo encoding
Symposium on VLSI Circuits, 2008Co-Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, T Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, E NagahamaAbstract:This paper describes a heterogeneous multi-Core processor (HMCP) Architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory Architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-Core having homogeneous processor Cores and dynamically reconfigurable processor (DRP) ACC Cores in a preliminary evaluation of the HMCP Architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.
Hiroaki Shikano - One of the best experts on this subject based on the ideXlab platform.
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heterogeneous multi Core Architecture that enables 54x aac lc stereo encoding
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, T Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, E NagahamaAbstract:This paper describes a heterogeneous multi-Core processor (HMCP) Architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory Architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-Core having homogeneous processor Cores and dynamically reconfigurable processor (DRP) ACC Cores in a preliminary evaluation of the HMCP Architecture. The performance evaluation revealed that 54times AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1- 2 min.
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heterogeneous multi Core Architecture that enables 54x aac lc stereo encoding
Symposium on VLSI Circuits, 2008Co-Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, T Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, E NagahamaAbstract:This paper describes a heterogeneous multi-Core processor (HMCP) Architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory Architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-Core having homogeneous processor Cores and dynamically reconfigurable processor (DRP) ACC Cores in a preliminary evaluation of the HMCP Architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.
Masafumi Onouchi - One of the best experts on this subject based on the ideXlab platform.
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heterogeneous multi Core Architecture that enables 54x aac lc stereo encoding
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, T Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, E NagahamaAbstract:This paper describes a heterogeneous multi-Core processor (HMCP) Architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory Architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-Core having homogeneous processor Cores and dynamically reconfigurable processor (DRP) ACC Cores in a preliminary evaluation of the HMCP Architecture. The performance evaluation revealed that 54times AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1- 2 min.
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heterogeneous multi Core Architecture that enables 54x aac lc stereo encoding
Symposium on VLSI Circuits, 2008Co-Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, T Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, E NagahamaAbstract:This paper describes a heterogeneous multi-Core processor (HMCP) Architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory Architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-Core having homogeneous processor Cores and dynamically reconfigurable processor (DRP) ACC Cores in a preliminary evaluation of the HMCP Architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.
Tatsuya Kamei - One of the best experts on this subject based on the ideXlab platform.
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heterogeneous multi Core Architecture that enables 54x aac lc stereo encoding
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, T Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, E NagahamaAbstract:This paper describes a heterogeneous multi-Core processor (HMCP) Architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory Architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-Core having homogeneous processor Cores and dynamically reconfigurable processor (DRP) ACC Cores in a preliminary evaluation of the HMCP Architecture. The performance evaluation revealed that 54times AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1- 2 min.
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heterogeneous multi Core Architecture that enables 54x aac lc stereo encoding
Symposium on VLSI Circuits, 2008Co-Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, T Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, E NagahamaAbstract:This paper describes a heterogeneous multi-Core processor (HMCP) Architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory Architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-Core having homogeneous processor Cores and dynamically reconfigurable processor (DRP) ACC Cores in a preliminary evaluation of the HMCP Architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.
Toshihiko Odaka - One of the best experts on this subject based on the ideXlab platform.
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heterogeneous multi Core Architecture that enables 54x aac lc stereo encoding
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, T Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, E NagahamaAbstract:This paper describes a heterogeneous multi-Core processor (HMCP) Architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory Architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-Core having homogeneous processor Cores and dynamically reconfigurable processor (DRP) ACC Cores in a preliminary evaluation of the HMCP Architecture. The performance evaluation revealed that 54times AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1- 2 min.
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heterogeneous multi Core Architecture that enables 54x aac lc stereo encoding
Symposium on VLSI Circuits, 2008Co-Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, T Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, E NagahamaAbstract:This paper describes a heterogeneous multi-Core processor (HMCP) Architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory Architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-Core having homogeneous processor Cores and dynamically reconfigurable processor (DRP) ACC Cores in a preliminary evaluation of the HMCP Architecture. The performance evaluation revealed that 54x AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1-2 min.