The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
A Virazel - One of the best experts on this subject based on the ideXlab platform.
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power supply noise aware workload assignments for homogeneous 3d mpsocs with thermal consideration
Asia and South Pacific Design Automation Conference, 2014Co-Authors: Yuanqing Cheng, Aida Todrisanial, A Bosio, Luigi Dilillo, P Girard, A VirazelAbstract:In order to improve performance and reduce cost, multi-processor system on chip (MPSoC) is increasingly becoming attractive. At the same time, 3D integration emerges as a promising technology for high density integration. 3D homogeneous MPSoCs combine the benefits of both. However, high current demand and large on-chip switching activity variations introduce severe power supply noises (PSN) for 3D MPSoCs, which can increase Critical Path Delay, and degrade chip performance and reliability. Meanwhile, thermal gradient should also be considered for 3D MPSoCs to avoid hot spots. In the paper, we investigate the PSN effects of different workloads and propose an effective PSN estimation method. Then, a heuristic workload assignment algorithm is proposed to suppress PSN under the given thermal constraint. The experimental results show that PSNs can be reduced significantly compared with thermal-balanced workload assignment scheme, and the system performance can be improved as well.
Takashi Sato - One of the best experts on this subject based on the ideXlab platform.
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efficient worst case timing analysis of Critical Path Delay under workload dependent aging degradation
Asia and South Pacific Design Automation Conference, 2018Co-Authors: Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi SatoAbstract:The effect of negative bias temperature instability (NBTI) varies significantly according to given workloads, and thus Path Delay degradation is strongly dependent on each use case. In this paper, we propose a subset simulation (SS) framework that efficiently and accurately finds the worst case workload and the failure probability covering various workloads. In the proposed method, workloads that yield worst aged Delay are efficiently generated by the NBTI-aware Markov chain Monte Carlo method. Through numerical experiments using benchmark circuits, the proposed method achieves up to 36 times speedup compared to the naive Monte Carlo method. From the result of the SS, feasible workload that gives worst aged Delay is obtained.
Miyuki Satou - One of the best experts on this subject based on the ideXlab platform.
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a 27 active power reduced 40 nm cmos multimedia soc with adaptive voltage scaling using distributed universal Delay lines
IEEE Journal of Solid-state Circuits, 2012Co-Authors: Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoshifumi Nishio, Tomohiro Iwashita, Miyuki SatouAbstract:AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal Delay line (UDL), rather than a replica Delay line, for monitoring the Critical Path Delay (TCRIT). The UDL can be used in any product without any need for customizing. In addition, averaging the results of distributed 4 monitors with a pitch of 3 mm in a chip can reduce errors due to within-die variation by half. With these techniques, proposed scheme produces equivalent or less error to TCRIT than does a conventional scheme that uses a single Critical Path replica as a Delay monitor, even with simple monitor design. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.
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a 27 active power reduced 40 nm cmos multimedia soc with adaptive voltage scaling using distributed universal Delay lines
Symposium on VLSI Circuits, 2011Co-Authors: Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoshifumi Nishio, Tomohiro Iwashita, Miyuki SatouAbstract:AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal Delay line (UDL), rather than a replica Delay line, for monitoring the Critical Path Delay (T CRIT ). The UDL can be used in any product without any need for customizing. The error to T CRIT is as small as that with replica Delay line. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.
Jinhua Hong - One of the best experts on this subject based on the ideXlab platform.
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rsa cryptosystem design based on the chinese remainder theorem
Asia and South Pacific Design Automation Conference, 2001Co-Authors: Jinhua HongAbstract:In this paper, we present the design and implementation of a systolic RSA cryptosystem based on a modified Montgomery's algorithm and the Chinese Remainder Theorem (CRT) technique. The CRT technique improves the throughput rate up to 4 times in the best case. The processing unit of the systolic array has 100% utilization because of the proposed block interleaving technique for multiplication and square operations in the modular exponentiation algorithm. For 512-bit inputs, the number of clock cycles needed for a modular exponentiation is about 0.13M to 0.24M. The Critical Path Delay is 6.13 ns using a 0.6 /spl mu/m CMOS technology. With a 150 MHz clock, we can achieve an encryption/decryption rate of about 328 to 578 Kb/s.
Yuanqing Cheng - One of the best experts on this subject based on the ideXlab platform.
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power supply noise aware workload assignments for homogeneous 3d mpsocs with thermal consideration
Asia and South Pacific Design Automation Conference, 2014Co-Authors: Yuanqing Cheng, Aida Todrisanial, A Bosio, Luigi Dilillo, P Girard, A VirazelAbstract:In order to improve performance and reduce cost, multi-processor system on chip (MPSoC) is increasingly becoming attractive. At the same time, 3D integration emerges as a promising technology for high density integration. 3D homogeneous MPSoCs combine the benefits of both. However, high current demand and large on-chip switching activity variations introduce severe power supply noises (PSN) for 3D MPSoCs, which can increase Critical Path Delay, and degrade chip performance and reliability. Meanwhile, thermal gradient should also be considered for 3D MPSoCs to avoid hot spots. In the paper, we investigate the PSN effects of different workloads and propose an effective PSN estimation method. Then, a heuristic workload assignment algorithm is proposed to suppress PSN under the given thermal constraint. The experimental results show that PSNs can be reduced significantly compared with thermal-balanced workload assignment scheme, and the system performance can be improved as well.